diff --git a/examples/nxp/mcx/build.zig b/examples/nxp/mcx/build.zig
index 0606d651c..783bba5aa 100644
--- a/examples/nxp/mcx/build.zig
+++ b/examples/nxp/mcx/build.zig
@@ -15,7 +15,11 @@ pub fn build(b: *std.Build) void {
     const frdm_mcxa153 = mb.ports.mcx.chips.mcxa153;
     const frdm_mcxn947 = mb.ports.mcx.chips.mcxn947;
 
+    const frdm_mcxa156 = mb.ports.mcx.boards.frdm_mcxa156;
+
     const available_examples = [_]Example{
+        .{ .name = "mcxa156_blinky", .target = frdm_mcxa156, .file = "src/mcxa156/blinky.zig" },
+        .{ .name = "mcxa156_clkout", .target = frdm_mcxa156, .file = "src/mcxa156/clkout.zig" },
         .{ .name = "mcxa153_blinky", .target = frdm_mcxa153, .file = "src/mcxa153_blinky.zig" },
         .{ .name = "mcxn947_blinky", .target = frdm_mcxn947, .file = "src/mcxn947_blinky.zig" },
         .{ .name = "gpio_input", .target = frdm_mcxa153, .file = "src/gpio_input.zig" },
diff --git a/examples/nxp/mcx/src/mcxa156/blinky.zig b/examples/nxp/mcx/src/mcxa156/blinky.zig
new file mode 100644
index 000000000..af14db45d
--- /dev/null
+++ b/examples/nxp/mcx/src/mcxa156/blinky.zig
@@ -0,0 +1,23 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const hal = microzig.hal;
+const board = microzig.board;
+
+const time = hal.time;
+
+pub const std_options = microzig.std_options(.{});
+
+comptime {
+    _ = microzig.export_startup();
+}
+
+pub fn main() !void {
+    board.Digital_RGB_Led.init();
+
+    while (true) {
+        for (0..7) |rgb| {
+            board.Digital_RGB_Led.set_color(@fromBackingInt(@intCast(rgb)));
+            time.sleep_ms(1000);
+        }
+    }
+}
diff --git a/examples/nxp/mcx/src/mcxa156/clkout.zig b/examples/nxp/mcx/src/mcxa156/clkout.zig
new file mode 100644
index 000000000..f54668171
--- /dev/null
+++ b/examples/nxp/mcx/src/mcxa156/clkout.zig
@@ -0,0 +1,23 @@
+pub const std_options = microzig.std_options(.{});
+
+const microzig = @import("microzig");
+const std = @import("std");
+const hal = microzig.hal;
+const Port = hal.port.Port;
+const clkout = hal.clkout;
+
+const PORT4: Port = @fromBackingInt(@intCast(4));
+
+comptime {
+    _ = microzig.export_startup();
+}
+
+pub fn main() !void {
+    PORT4.init();
+    clkout.enable(.P4_2, .SLOW_CLK, 0);
+    try hal.syscon.clock_init(.{
+        .frohf = .{ .freq = .@"96Mhz", .fro_hf_div = 1 },
+        .ahb_div = 4,
+    });
+    while (true) {}
+}
diff --git a/port/nxp/mcx/build.zig b/port/nxp/mcx/build.zig
index 1e1d91af4..cbbc10825 100644
--- a/port/nxp/mcx/build.zig
+++ b/port/nxp/mcx/build.zig
@@ -4,12 +4,27 @@ const microzig = @import("microzig/build-internals");
 const Self = @This();
 
 chips: struct {
+    //MCX-A 153/152/143/142/132/133
     mcxa153: *const microzig.Target,
+
+    //MCX-A 154/155/156/144/145/146
+    //mcxa144: *const microzig.Target, TODO
+    //mcxa145: *const microzig.Target, TODO
+    //mcxa146: *const microzig.Target, TODO
+    mcxa154: *const microzig.Target,
+    mcxa155: *const microzig.Target,
+    mcxa156: *const microzig.Target,
+
+    //MCX-N low density
+    //mcxn256: *const microzig.Target, //TODO
+
+    //MCX-N HIGH density
     mcxn947: *const microzig.Target,
 },
 
 boards: struct {
     frdm_mcxa153: *const microzig.Target,
+    frdm_mcxa156: *const microzig.Target,
     frdm_mcxn947: *const microzig.Target,
 },
 
@@ -18,6 +33,69 @@ pub fn init(dep: *std.Build.Dependency) ?Self {
 
     const mcux_soc_svd = b.lazyDependency("mcux-soc-svd", .{}) orelse return null;
 
+    const chip_mcxa154: microzig.Target = .{
+        .dep = dep,
+        .preferred_binary_format = .elf,
+        .zig_target = .{
+            .cpu_arch = .thumb,
+            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 },
+            .os_tag = .freestanding,
+            .abi = .eabihf,
+        },
+        .chip = .{
+            .name = "MCXA154",
+            .register_definition = .{ .svd = mcux_soc_svd.path("MCXA154/MCXA154.xml") },
+            .memory_regions = &.{
+                .{ .tag = .flash, .offset = 0x00000000, .length = 256 * 1024, .access = .rx },
+                .{ .tag = .ram, .offset = 0x20000000, .length = 64 * 1024, .access = .rw },
+                .{ .tag = .ram, .offset = 0x2001E000, .length = 8 * 1024, .access = .rw, .name = "ECC" },
+            },
+        },
+        .hal = .{ .root_source_file = b.path("src/mcxa_15x/hal.zig") },
+    };
+
+    const chip_mcxa155: microzig.Target = .{
+        .dep = dep,
+        .preferred_binary_format = .elf,
+        .zig_target = .{
+            .cpu_arch = .thumb,
+            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 },
+            .os_tag = .freestanding,
+            .abi = .eabihf,
+        },
+        .chip = .{
+            .name = "MCXA155",
+            .register_definition = .{ .svd = mcux_soc_svd.path("MCXA155/MCXA155.xml") },
+            .memory_regions = &.{
+                .{ .tag = .flash, .offset = 0x00000000, .length = 512 * 1024, .access = .rx },
+                .{ .tag = .ram, .offset = 0x20000000, .length = 96 * 1024, .access = .rw },
+                .{ .tag = .ram, .offset = 0x2001E000, .length = 8 * 1024, .access = .rw, .name = "ECC" },
+            },
+        },
+        .hal = .{ .root_source_file = b.path("src/mcxa_15x/hal.zig") },
+    };
+
+    const chip_mcxa156: microzig.Target = .{
+        .dep = dep,
+        .preferred_binary_format = .elf,
+        .zig_target = .{
+            .cpu_arch = .thumb,
+            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m33 },
+            .os_tag = .freestanding,
+            .abi = .eabi,
+        },
+        .chip = .{
+            .name = "MCXA156",
+            .register_definition = .{ .svd = mcux_soc_svd.path("MCXA156/MCXA156.xml") },
+            .memory_regions = &.{
+                .{ .tag = .flash, .offset = 0x00000000, .length = 1024 * 1024, .access = .rx },
+                .{ .tag = .ram, .offset = 0x20000000, .length = 120 * 1024, .access = .rw },
+                .{ .tag = .ram, .offset = 0x2001E000, .length = 8 * 1024, .access = .rw, .name = "ECC" },
+            },
+        },
+        .hal = .{ .root_source_file = b.path("src/mcxa_15x/hal.zig") },
+    };
+
     const chip_mcxa153: microzig.Target = .{
         .dep = dep,
         .preferred_binary_format = .elf,
@@ -63,14 +141,36 @@ pub fn init(dep: *std.Build.Dependency) ?Self {
     };
 
     return .{
-        .chips = .{ .mcxa153 = chip_mcxa153.derive(.{}), .mcxn947 = chip_mcxn947.derive(.{}) },
-        .boards = .{ .frdm_mcxa153 = chip_mcxa153.derive(.{
-            .board = .{
-                .name = "FRDM Development Board for MCX A153",
-                .url = "https://www.nxp.com/part/FRDM-MCXA153",
-                .root_source_file = b.path("src/boards/frdm_mcxa153.zig"),
-            },
-        }), .frdm_mcxn947 = chip_mcxn947.derive(.{ .board = .{ .name = "FRDM Development Board for MCX N947", .url = "https://www.nxp.com/part/FRDM-MCXN947", .root_source_file = b.path("src/boards/frdm_mcxn947.zig") } }) },
+        .chips = .{
+            .mcxa153 = chip_mcxa153.derive(.{}),
+            .mcxa154 = chip_mcxa154.derive(.{}),
+            .mcxa155 = chip_mcxa155.derive(.{}),
+            .mcxa156 = chip_mcxa156.derive(.{}),
+            .mcxn947 = chip_mcxn947.derive(.{}),
+        },
+        .boards = .{
+            .frdm_mcxa153 = chip_mcxa153.derive(.{
+                .board = .{
+                    .name = "FRDM Development Board for MCX A153",
+                    .url = "https://www.nxp.com/part/FRDM-MCXA153",
+                    .root_source_file = b.path("src/boards/frdm_mcxa153.zig"),
+                },
+            }),
+            .frdm_mcxn947 = chip_mcxn947.derive(.{
+                .board = .{
+                    .name = "FRDM Development Board for MCX N947",
+                    .url = "https://www.nxp.com/part/FRDM-MCXN947",
+                    .root_source_file = b.path("src/boards/frdm_mcxn947.zig"),
+                },
+            }),
+            .frdm_mcxa156 = chip_mcxa156.derive(.{
+                .board = .{
+                    .name = "FRDM Development Board for MCX A156",
+                    .url = "https://www.nxp.com/part/FRDM-MCXA156",
+                    .root_source_file = b.path("src/boards/frdm_mcxa156.zig"),
+                },
+            }),
+        },
     };
 }
 
diff --git a/port/nxp/mcx/src/boards/frdm_mcxa156.zig b/port/nxp/mcx/src/boards/frdm_mcxa156.zig
new file mode 100644
index 000000000..349dce40d
--- /dev/null
+++ b/port/nxp/mcx/src/boards/frdm_mcxa156.zig
@@ -0,0 +1,45 @@
+const microzig = @import("microzig");
+const hal = microzig.hal;
+//TODO: expose RGB Led pins as PWM
+
+const Color = enum(u3) {
+    // RGB LED is active-low
+    off = 0b111,
+    blue = 0b110,
+    green = 0b101,
+    cyan = 0b100,
+    red = 0b011,
+    magenta = 0b010,
+    yellow = 0b001,
+    white = 0b000,
+};
+
+const RGB_Pin = packed struct(u3) {
+    B: u1,
+    G: u1,
+    R: u1,
+};
+
+//expose the RGB led pins as GPIOs
+pub const Digital_RGB_Led = struct {
+    const port3 = hal.port.num(3);
+    const R = hal.gpio.from_pin(.P3_12);
+    const G = hal.gpio.from_pin(.P3_13);
+    const B = hal.gpio.from_pin(.P3_0);
+
+    pub fn init() void {
+        port3.init();
+        R.init();
+        R.set_direction(.out);
+        G.set_direction(.out);
+        B.set_direction(.out);
+    }
+
+    pub fn set_color(c: Color) void {
+        const P: RGB_Pin = @bitCast(c);
+
+        R.put(P.R);
+        G.put(P.G);
+        B.put(P.B);
+    }
+};
diff --git a/port/nxp/mcx/src/mcxa_15x/hal.zig b/port/nxp/mcx/src/mcxa_15x/hal.zig
new file mode 100644
index 000000000..45eea642f
--- /dev/null
+++ b/port/nxp/mcx/src/mcxa_15x/hal.zig
@@ -0,0 +1,15 @@
+pub const syscon = @import("hal/syscon.zig");
+pub const clkout = @import("hal/clkout.zig");
+pub const port = @import("hal/port.zig");
+pub const gpio = @import("hal/gpio.zig");
+pub const ostime = @import("hal/ostimer.zig");
+
+pub const time = struct {
+    pub const get_time_since_boot = ostime.get_time_since_boot;
+    pub const sleep_ms = ostime.sleep_ms;
+    pub const sleep_us = ostime.sleep_us;
+};
+
+pub fn init() void {
+    ostime.init();
+}
diff --git a/port/nxp/mcx/src/mcxa_15x/hal/clkout.zig b/port/nxp/mcx/src/mcxa_15x/hal/clkout.zig
new file mode 100644
index 000000000..2a4027e41
--- /dev/null
+++ b/port/nxp/mcx/src/mcxa_15x/hal/clkout.zig
@@ -0,0 +1,45 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const syscon = @import("syscon.zig");
+const mapper = @import("mapper.zig");
+const port = @import("port.zig");
+const meta = @import("meta_utils.zig");
+
+const MRCC0 = microzig.chip.peripherals.MRCC0;
+
+const Clock_Source = enum(u3) {
+    FRO_12M = 0,
+    FRO_HF_DIV = 1,
+    CLK_IN = 2,
+    CLK_16K = 3,
+    SLOW_CLK = 6,
+    no_Clock = 7,
+};
+
+pub fn enable(comptime pin: mapper.PIN, src: Clock_Source, div: u4) void {
+    set_pin(pin);
+    syscon.unlock_clock_configuration();
+    defer syscon.freeze_clock_configuration();
+
+    MRCC0.MRCC_CLKOUT_CLKSEL.modify_one("MUX", @fromBackingInt(@intCast(@backingInt(src))));
+
+    MRCC0.MRCC_CLKOUT_CLKDIV.write(.{
+        .DIV = div,
+        .HALT = .OFF,
+        .RESET = .OFF,
+    });
+
+    MRCC0.MRCC_CLKOUT_CLKDIV.write(.{
+        .DIV = div,
+        .HALT = .ON,
+        .RESET = .ON,
+    });
+
+    while (MRCC0.MRCC_CLKOUT_CLKDIV.read().UNSTAB == .OFF) {}
+}
+
+fn set_pin(comptime pin: mapper.PIN) void {
+    port.Port.configure_pin(pin, .{
+        .MUX = comptime meta.check_mux(pin, .CLKOUT_clkout),
+    });
+}
diff --git a/port/nxp/mcx/src/mcxa_15x/hal/gpio.zig b/port/nxp/mcx/src/mcxa_15x/hal/gpio.zig
new file mode 100644
index 000000000..06ce22fc5
--- /dev/null
+++ b/port/nxp/mcx/src/mcxa_15x/hal/gpio.zig
@@ -0,0 +1,125 @@
+const microzig = @import("microzig");
+const syscon = @import("./syscon.zig");
+const mapper = @import("mapper.zig");
+
+const PIN = mapper.PIN;
+const PIN_MAP = mapper.PIN_MAP;
+
+const chip = microzig.chip;
+
+pub fn from_pin(pin: mapper.PIN) GPIO {
+    return @bitCast(pin);
+}
+
+pub const GPIO = enum(u8) {
+    _,
+
+    pub fn init(comptime gpio: GPIO) void {
+        const map: PIN_MAP = @bitCast(@backingInt(gpio));
+        const tag = switch (map.port) {
+            0 => .GPIO0,
+            1 => .GPIO1,
+            2 => .GPIO2,
+            3 => .GPIO3,
+            4 => .GPIO4,
+            else => unreachable,
+        };
+
+        syscon.reset_release(tag);
+        syscon.enable_clock(tag);
+    }
+
+    pub fn put(gpio: GPIO, output: u1) void {
+        const regs = gpio.get_regs();
+        const old: u32 = regs.PDOR.raw;
+        const new = @as(u32, output) << gpio.get_pin();
+
+        regs.PDOR.write_raw(old & ~gpio.get_mask() | new);
+    }
+
+    pub fn get(gpio: GPIO) bool {
+        const regs = gpio.get_regs();
+
+        return regs.PDIR.raw >> gpio.get_pin() & 1 != 0;
+    }
+
+    pub fn toggle(gpio: GPIO) void {
+        const regs = gpio.get_regs();
+        const old: u32 = regs.PTOR.raw;
+
+        regs.PTOR.write_raw(old | gpio.get_mask());
+    }
+
+    pub fn set_direction(gpio: GPIO, direction: Direction) void {
+        const regs = gpio.get_regs();
+        const old: u32 = regs.PDDR.raw;
+        const new = @as(u32, @backingInt(direction)) << gpio.get_pin();
+
+        regs.PDDR.write_raw(old & ~gpio.get_mask() | new);
+    }
+
+    pub fn set_interrupt_config(gpio: GPIO, trigger: InterruptConfig) void {
+        const regs = gpio.get_regs();
+        const irqc = @as(u32, @backingInt(trigger)) << 16;
+        const isf = @as(u32, 1) << 24;
+
+        regs.ICR[gpio.get_pin()].write_raw(irqc | isf);
+    }
+
+    pub fn get_interrupt_flag(gpio: GPIO) bool {
+        const regs = gpio.get_regs();
+
+        return regs.ISFR0.raw >> gpio.get_pin() & 1 != 0;
+    }
+
+    pub fn clear_interrupt_flag(gpio: GPIO) void {
+        const regs = gpio.get_regs();
+        const old: u32 = regs.ISFR0.raw;
+
+        regs.ISFR0.write_raw(old | gpio.get_mask());
+    }
+
+    fn get_regs(gpio: GPIO) *volatile chip.types.peripherals.GPIO0 {
+        return switch (gpio.get_n()) {
+            0 => chip.peripherals.GPIO0,
+            1 => chip.peripherals.GPIO1,
+            2 => chip.peripherals.GPIO2,
+            3 => chip.peripherals.GPIO3,
+            4 => chip.peripherals.GPIO4,
+            else => unreachable,
+        };
+    }
+
+    pub inline fn get_n(gpio: GPIO) u3 {
+        const map: PIN_MAP = @bitCast(@backingInt(gpio));
+        return map.port;
+    }
+
+    pub inline fn get_pin(gpio: GPIO) u5 {
+        const map: PIN_MAP = @bitCast(@backingInt(gpio));
+        return map.pin;
+    }
+
+    inline fn get_mask(gpio: GPIO) u32 {
+        return @as(u32, 1) << gpio.get_pin();
+    }
+};
+
+const Direction = enum(u1) { in, out };
+
+const InterruptConfig = enum(u4) {
+    disabled = 0,
+    dma_rising_edge = 1,
+    dma_falling_edge = 2,
+    dma_either_edge = 3,
+    flag_rising_edge = 5,
+    flag_falling_edge = 6,
+    flag_either_edge = 7,
+    interrupt_logic_zero = 8,
+    interrupt_rising_edge = 9,
+    interrupt_falling_edge = 10,
+    interrupt_either_edge = 11,
+    interrupt_logic_one = 12,
+    active_high_trigger_output_enable = 13,
+    active_low_trigger_output_enable = 14,
+};
diff --git a/port/nxp/mcx/src/mcxa_15x/hal/mapper.zig b/port/nxp/mcx/src/mcxa_15x/hal/mapper.zig
new file mode 100644
index 000000000..63572962f
--- /dev/null
+++ b/port/nxp/mcx/src/mcxa_15x/hal/mapper.zig
@@ -0,0 +1,2039 @@
+const Self = @This();
+const std = @import("std");
+pub const PORTS = struct {
+    pub const PORT0 = 0b00000000111111110000000001001111;
+    pub const PORT1 = 0b11100000000000001111111111111111;
+    pub const PORT2 = 0b00000000101110111011110011111111;
+    pub const PORT3 = 0b11111000011111111111111111000111;
+    pub const PORT4 = 0b00000000000000000000000011111100;
+};
+
+pub const PIN_MAP = packed struct(u8) {
+    pin: u5,
+    port: u3,
+};
+
+pub const PIN = enum(u8) {
+    P0_0 = 0b00000000,
+    P0_1 = 0b00000001,
+    P0_16 = 0b00010000,
+    P0_17 = 0b00010001,
+    P0_18 = 0b00010010,
+    P0_19 = 0b00010011,
+    P0_2 = 0b00000010,
+    P0_20 = 0b00010100,
+    P0_21 = 0b00010101,
+    P0_22 = 0b00010110,
+    P0_23 = 0b00010111,
+    P0_3 = 0b00000011,
+    P0_6 = 0b00000110,
+    P1_0 = 0b00100000,
+    P1_1 = 0b00100001,
+    P1_10 = 0b00101010,
+    P1_11 = 0b00101011,
+    P1_12 = 0b00101100,
+    P1_13 = 0b00101101,
+    P1_14 = 0b00101110,
+    P1_15 = 0b00101111,
+    P1_2 = 0b00100010,
+    P1_29 = 0b00111101,
+    P1_3 = 0b00100011,
+    P1_30 = 0b00111110,
+    P1_31 = 0b00111111,
+    P1_4 = 0b00100100,
+    P1_5 = 0b00100101,
+    P1_6 = 0b00100110,
+    P1_7 = 0b00100111,
+    P1_8 = 0b00101000,
+    P1_9 = 0b00101001,
+    P2_0 = 0b01000000,
+    P2_1 = 0b01000001,
+    P2_10 = 0b01001010,
+    P2_11 = 0b01001011,
+    P2_12 = 0b01001100,
+    P2_13 = 0b01001101,
+    P2_15 = 0b01001111,
+    P2_16 = 0b01010000,
+    P2_17 = 0b01010001,
+    P2_19 = 0b01010011,
+    P2_2 = 0b01000010,
+    P2_20 = 0b01010100,
+    P2_21 = 0b01010101,
+    P2_23 = 0b01010111,
+    P2_3 = 0b01000011,
+    P2_4 = 0b01000100,
+    P2_5 = 0b01000101,
+    P2_6 = 0b01000110,
+    P2_7 = 0b01000111,
+    P3_0 = 0b01100000,
+    P3_1 = 0b01100001,
+    P3_10 = 0b01101010,
+    P3_11 = 0b01101011,
+    P3_12 = 0b011_01100,
+    P3_13 = 0b01101101,
+    P3_14 = 0b01101110,
+    P3_15 = 0b01101111,
+    P3_16 = 0b01110000,
+    P3_17 = 0b01110001,
+    P3_18 = 0b01110010,
+    P3_19 = 0b01110011,
+    P3_2 = 0b01100010,
+    P3_20 = 0b01110100,
+    P3_21 = 0b01110101,
+    P3_22 = 0b01110110,
+    P3_27 = 0b01111011,
+    P3_28 = 0b01111100,
+    P3_29 = 0b01111101,
+    P3_30 = 0b01111110,
+    P3_31 = 0b01111111,
+    P3_6 = 0b01100110,
+    P3_7 = 0b01100111,
+    P3_8 = 0b01101000,
+    P3_9 = 0b01101001,
+    P4_2 = 0b10000010,
+    P4_3 = 0b10000011,
+    P4_4 = 0b10000100,
+    P4_5 = 0b10000101,
+    P4_6 = 0b10000110,
+    P4_7 = 0b10000111,
+
+    pub fn mux(comptime pin: PIN) type {
+        return @field(Self, @tagName(pin));
+    }
+
+    pub inline fn map(self: PIN) PIN_MAP {
+        return @bitCast(self);
+    }
+};
+
+pub const PERIPHERALS = enum(u16) {
+    ADC0,
+    ADC1,
+    AOI0,
+    AOI1,
+    CAN0,
+    CDOG,
+    CLKOUT,
+    CMC,
+    CMP0,
+    CMP1,
+    CRC0,
+    CT,
+    CTIMER0,
+    CTIMER1,
+    CTIMER2,
+    CTIMER3,
+    CTIMER4,
+    DAC0,
+    DBGMAILBOX,
+    DMA0,
+    EDMA_0_TCD0,
+    EIM0,
+    ERM0,
+    FLEXIO0,
+    FLEXPWM0,
+    FLEXPWM1,
+    FMC0,
+    FMU0,
+    FREQME0,
+    GLIKEY0,
+    GPIO0,
+    GPIO1,
+    GPIO2,
+    GPIO3,
+    GPIO4,
+    I3C0,
+    LPI2C0,
+    LPI2C1,
+    LPI2C2,
+    LPI2C3,
+    LPSPI0,
+    LPSPI1,
+    LPTMR0,
+    LPUART0,
+    LPUART1,
+    LPUART2,
+    LPUART3,
+    LPUART4,
+    MBC0,
+    MRCC0,
+    NVIC,
+    OPAMP0,
+    OSTIMER0,
+    PORT0,
+    PORT1,
+    PORT2,
+    PORT3,
+    PORT4,
+    QDC0,
+    QDC1,
+    RESET,
+    SAU,
+    SCB,
+    SCG0,
+    SCnSCB,
+    SPC0,
+    SYSCON,
+    SysTick,
+    TRIG,
+    USB0,
+    UTICK0,
+    VBAT0,
+    WAKETIMER0,
+    WUU0,
+    WWDT0,
+};
+
+pub const SIGNALS = enum(u16) {
+    ADC0_a0,
+    ADC0_a1,
+    ADC0_a10,
+    ADC0_a11,
+    ADC0_a12,
+    ADC0_a13,
+    ADC0_a14,
+    ADC0_a15,
+    ADC0_a16,
+    ADC0_a17,
+    ADC0_a18,
+    ADC0_a19,
+    ADC0_a2,
+    ADC0_a20,
+    ADC0_a21,
+    ADC0_a22,
+    ADC0_a23,
+    ADC0_a4,
+    ADC0_a5,
+    ADC0_a6,
+    ADC0_a7,
+    ADC0_a8,
+    ADC0_a9,
+    ADC1_a0,
+    ADC1_a1,
+    ADC1_a10,
+    ADC1_a11,
+    ADC1_a12,
+    ADC1_a13,
+    ADC1_a2,
+    ADC1_a20,
+    ADC1_a21,
+    ADC1_a22,
+    ADC1_a3,
+    ADC1_a4,
+    ADC1_a5,
+    ADC1_a6,
+    ADC1_a7,
+    ADC1_a8,
+    ADC1_a9,
+    CAN0_rxd,
+    CAN0_txd,
+    CLKOUT_clkout,
+    CMP0_in0,
+    CMP0_in1,
+    CMP0_in2,
+    CMP0_in3,
+    CMP0_out,
+    CMP1_in0,
+    CMP1_in1,
+    CMP1_in2,
+    CMP1_in3,
+    CMP1_out,
+    CT_inp0,
+    CT_inp1,
+    CT_inp10,
+    CT_inp11,
+    CT_inp12,
+    CT_inp13,
+    CT_inp14,
+    CT_inp15,
+    CT_inp16,
+    CT_inp17,
+    CT_inp18,
+    CT_inp19,
+    CT_inp2,
+    CT_inp3,
+    CT_inp4,
+    CT_inp5,
+    CT_inp6,
+    CT_inp7,
+    CT_inp8,
+    CT_inp9,
+    CTIMER0_mat0,
+    CTIMER0_mat1,
+    CTIMER0_mat2,
+    CTIMER0_mat3,
+    CTIMER1_mat0,
+    CTIMER1_mat1,
+    CTIMER1_mat2,
+    CTIMER1_mat3,
+    CTIMER2_mat0,
+    CTIMER2_mat1,
+    CTIMER2_mat2,
+    CTIMER2_mat3,
+    CTIMER3_mat0,
+    CTIMER3_mat1,
+    CTIMER3_mat2,
+    CTIMER3_mat3,
+    CTIMER4_mat0,
+    CTIMER4_mat1,
+    CTIMER4_mat2,
+    CTIMER4_mat3,
+    DAC0_out,
+    FLEXIO0_d0,
+    FLEXIO0_d1,
+    FLEXIO0_d10,
+    FLEXIO0_d11,
+    FLEXIO0_d12,
+    FLEXIO0_d13,
+    FLEXIO0_d14,
+    FLEXIO0_d15,
+    FLEXIO0_d16,
+    FLEXIO0_d17,
+    FLEXIO0_d18,
+    FLEXIO0_d19,
+    FLEXIO0_d2,
+    FLEXIO0_d20,
+    FLEXIO0_d21,
+    FLEXIO0_d22,
+    FLEXIO0_d23,
+    FLEXIO0_d24,
+    FLEXIO0_d25,
+    FLEXIO0_d26,
+    FLEXIO0_d27,
+    FLEXIO0_d28,
+    FLEXIO0_d29,
+    FLEXIO0_d3,
+    FLEXIO0_d30,
+    FLEXIO0_d31,
+    FLEXIO0_d4,
+    FLEXIO0_d5,
+    FLEXIO0_d6,
+    FLEXIO0_d7,
+    FLEXIO0_d8,
+    FLEXIO0_d9,
+    I3C0_pur,
+    I3C0_scl,
+    I3C0_sda,
+    LPI2C0_hreq,
+    LPI2C0_scl,
+    LPI2C0_scls,
+    LPI2C0_sda,
+    LPI2C0_sdas,
+    LPI2C1_scl,
+    LPI2C1_scls,
+    LPI2C1_sda,
+    LPI2C1_sdas,
+    LPI2C2_hreq,
+    LPI2C2_scl,
+    LPI2C2_scls,
+    LPI2C2_sda,
+    LPI2C2_sdas,
+    LPI2C3_hreq,
+    LPI2C3_scl,
+    LPI2C3_scls,
+    LPI2C3_sda,
+    LPI2C3_sdas,
+    LPSPI0_pcs0,
+    LPSPI0_pcs1,
+    LPSPI0_pcs2,
+    LPSPI0_pcs3,
+    LPSPI0_sck,
+    LPSPI0_sdi,
+    LPSPI0_sdo,
+    LPSPI1_pcs0,
+    LPSPI1_pcs1,
+    LPSPI1_pcs2,
+    LPSPI1_pcs3,
+    LPSPI1_sck,
+    LPSPI1_sdi,
+    LPSPI1_sdo,
+    LPUART0_cts,
+    LPUART0_rts,
+    LPUART0_rxd,
+    LPUART0_txd,
+    LPUART1_cts,
+    LPUART1_rts,
+    LPUART1_rxd,
+    LPUART1_txd,
+    LPUART2_cts,
+    LPUART2_rts,
+    LPUART2_rxd,
+    LPUART2_txd,
+    LPUART3_cts,
+    LPUART3_rts,
+    LPUART3_rxd,
+    LPUART3_txd,
+    LPUART4_cts,
+    LPUART4_rts,
+    LPUART4_rxd,
+    LPUART4_txd,
+    OPAMP0_inn,
+    OPAMP0_inp0,
+    OPAMP0_out,
+    RESET_btn,
+    TRIG_in0,
+    TRIG_in1,
+    TRIG_in10,
+    TRIG_in11,
+    TRIG_in2,
+    TRIG_in3,
+    TRIG_in4,
+    TRIG_in5,
+    TRIG_in6,
+    TRIG_in7,
+    TRIG_in8,
+    TRIG_in9,
+    TRIG_out0,
+    TRIG_out1,
+    TRIG_out2,
+    TRIG_out3,
+    TRIG_out4,
+    TRIG_out5,
+    TRIG_out6,
+    TRIG_out7,
+    USB0_det,
+
+    pub fn pins(comptime signal: SIGNALS) type {
+        var iter = std.mem.splitAny(u8, @tagName(signal), "_");
+        const peri = iter.next().?;
+        const sig = iter.next().?;
+
+        return @field(@field(Self, peri), sig);
+    }
+};
+
+pub const ADC0 = struct {
+    pub const a0 = struct {
+        pub const P2_0 = 0;
+    };
+    pub const a1 = struct {
+        pub const P2_1 = 0;
+    };
+    pub const a10 = struct {
+        pub const P0_20 = 0;
+    };
+    pub const a11 = struct {
+        pub const P0_21 = 0;
+    };
+    pub const a12 = struct {
+        pub const P0_22 = 0;
+    };
+    pub const a13 = struct {
+        pub const P0_23 = 0;
+    };
+    pub const a14 = struct {
+        pub const P0_3 = 0;
+    };
+    pub const a15 = struct {
+        pub const P0_6 = 0;
+    };
+    pub const a16 = struct {
+        pub const P1_0 = 0;
+    };
+    pub const a17 = struct {
+        pub const P1_1 = 0;
+    };
+    pub const a18 = struct {
+        pub const P1_2 = 0;
+    };
+    pub const a19 = struct {
+        pub const P1_3 = 0;
+    };
+    pub const a2 = struct {
+        pub const P2_15 = 0;
+    };
+    pub const a20 = struct {
+        pub const P1_4 = 0;
+    };
+    pub const a21 = struct {
+        pub const P1_5 = 0;
+    };
+    pub const a22 = struct {
+        pub const P1_6 = 0;
+    };
+    pub const a23 = struct {
+        pub const P1_7 = 0;
+    };
+    pub const a4 = struct {
+        pub const P2_2 = 0;
+    };
+    pub const a5 = struct {
+        pub const P2_12 = 0;
+    };
+    pub const a6 = struct {
+        pub const P2_16 = 0;
+    };
+    pub const a7 = struct {
+        pub const P2_7 = 0;
+    };
+    pub const a8 = struct {
+        pub const P0_18 = 0;
+    };
+    pub const a9 = struct {
+        pub const P0_19 = 0;
+    };
+};
+
+pub const ADC1 = struct {
+    pub const a0 = struct {
+        pub const P2_4 = 0;
+    };
+    pub const a1 = struct {
+        pub const P2_5 = 0;
+    };
+    pub const a10 = struct {
+        pub const P1_12 = 0;
+    };
+    pub const a11 = struct {
+        pub const P1_13 = 0;
+    };
+    pub const a12 = struct {
+        pub const P1_14 = 0;
+    };
+    pub const a13 = struct {
+        pub const P1_15 = 0;
+    };
+    pub const a2 = struct {
+        pub const P2_19 = 0;
+    };
+    pub const a20 = struct {
+        pub const P3_31 = 0;
+    };
+    pub const a21 = struct {
+        pub const P3_30 = 0;
+    };
+    pub const a22 = struct {
+        pub const P3_29 = 0;
+    };
+    pub const a3 = struct {
+        pub const P2_6 = 0;
+    };
+    pub const a4 = struct {
+        pub const P2_3 = 0;
+    };
+    pub const a5 = struct {
+        pub const P2_13 = 0;
+    };
+    pub const a6 = struct {
+        pub const P2_17 = 0;
+    };
+    pub const a7 = struct {
+        pub const P2_7 = 0;
+    };
+    pub const a8 = struct {
+        pub const P1_10 = 0;
+    };
+    pub const a9 = struct {
+        pub const P1_11 = 0;
+    };
+};
+
+pub const CAN0 = struct {
+    pub const rxd = struct {
+        pub const P1_11 = 11;
+        pub const P1_12 = 11;
+        pub const P2_12 = 11;
+        pub const P1_3 = 11;
+        pub const P1_7 = 11;
+    };
+    pub const txd = struct {
+        pub const P1_10 = 11;
+        pub const P1_13 = 11;
+        pub const P2_13 = 11;
+        pub const P1_2 = 11;
+        pub const P1_6 = 11;
+    };
+};
+
+pub const CLKOUT = struct {
+    pub const clkout = struct {
+        pub const P4_2 = 1;
+        pub const P3_8 = 12;
+        pub const P3_6 = 1;
+        pub const P0_6 = 12;
+    };
+};
+
+pub const CMP0 = struct {
+    pub const in0 = struct {
+        pub const P2_2 = 0;
+    };
+    pub const in1 = struct {
+        pub const P1_3 = 0;
+    };
+    pub const in2 = struct {
+        pub const P1_4 = 0;
+    };
+    pub const in3 = struct {
+        pub const P1_0 = 0;
+    };
+    pub const out = struct {
+        pub const P0_3 = 8;
+        pub const P0_18 = 8;
+    };
+};
+
+pub const CMP1 = struct {
+    pub const in0 = struct {
+        pub const P2_3 = 0;
+    };
+    pub const in1 = struct {
+        pub const P0_3 = 0;
+    };
+    pub const in2 = struct {
+        pub const P1_5 = 0;
+    };
+    pub const in3 = struct {
+        pub const P1_1 = 0;
+    };
+    pub const out = struct {
+        pub const P0_6 = 8;
+        pub const P0_19 = 8;
+    };
+};
+
+pub const CT = struct {
+    pub const inp0 = struct {
+        pub const P0_0 = 4;
+        pub const P0_20 = 4;
+        pub const P1_2 = 5;
+    };
+    pub const inp1 = struct {
+        pub const P0_1 = 4;
+        pub const P0_21 = 4;
+        pub const P1_3 = 5;
+    };
+    pub const inp10 = struct {
+        pub const P1_14 = 4;
+        pub const P3_22 = 4;
+    };
+    pub const inp11 = struct {
+        pub const P1_15 = 4;
+    };
+    pub const inp12 = struct {
+        pub const P2_2 = 4;
+        pub const P3_28 = 4;
+    };
+    pub const inp13 = struct {
+        pub const P2_3 = 4;
+        pub const P3_27 = 4;
+    };
+    pub const inp14 = struct {
+        pub const P2_4 = 4;
+    };
+    pub const inp15 = struct {
+        pub const P2_5 = 4;
+    };
+    pub const inp16 = struct {
+        pub const P1_30 = 4;
+        pub const P2_0 = 4;
+        pub const P3_0 = 4;
+    };
+    pub const inp17 = struct {
+        pub const P1_31 = 4;
+        pub const P2_1 = 4;
+        pub const P3_1 = 4;
+    };
+    pub const inp18 = struct {
+        pub const P2_6 = 4;
+    };
+    pub const inp19 = struct {
+        pub const P2_7 = 4;
+    };
+    pub const inp2 = struct {
+        pub const P0_6 = 4;
+        pub const P0_22 = 4;
+    };
+    pub const inp3 = struct {
+        pub const P3_29 = 4;
+        pub const P0_23 = 4;
+    };
+    pub const inp4 = struct {
+        pub const P3_8 = 4;
+        pub const P1_0 = 4;
+    };
+    pub const inp5 = struct {
+        pub const P3_9 = 4;
+        pub const P1_1 = 4;
+    };
+    pub const inp6 = struct {
+        pub const P4_6 = 4;
+        pub const P3_14 = 4;
+        pub const P1_6 = 4;
+    };
+    pub const inp7 = struct {
+        pub const P4_7 = 4;
+        pub const P3_15 = 4;
+        pub const P1_7 = 4;
+    };
+    pub const inp8 = struct {
+        pub const P1_8 = 4;
+        pub const P3_16 = 4;
+    };
+    pub const inp9 = struct {
+        pub const P1_9 = 4;
+        pub const P3_17 = 4;
+    };
+};
+
+pub const CTIMER0 = struct {
+    pub const mat0 = struct {
+        pub const P2_12 = 5;
+        pub const P0_2 = 4;
+        pub const P0_16 = 4;
+        pub const P0_22 = 5;
+    };
+    pub const mat1 = struct {
+        pub const P2_13 = 5;
+        pub const P0_3 = 4;
+        pub const P0_17 = 4;
+        pub const P0_23 = 5;
+    };
+    pub const mat2 = struct {
+        pub const P1_8 = 5;
+        pub const P2_15 = 5;
+        pub const P2_16 = 5;
+        pub const P3_30 = 4;
+        pub const P0_18 = 4;
+        pub const P1_0 = 5;
+    };
+    pub const mat3 = struct {
+        pub const P1_9 = 5;
+        pub const P2_17 = 5;
+        pub const P3_31 = 4;
+        pub const P0_19 = 4;
+        pub const P1_1 = 5;
+    };
+};
+
+pub const CTIMER1 = struct {
+    pub const mat0 = struct {
+        pub const P2_4 = 5;
+        pub const P3_10 = 4;
+        pub const P1_2 = 4;
+    };
+    pub const mat1 = struct {
+        pub const P2_5 = 5;
+        pub const P3_11 = 4;
+        pub const P1_3 = 4;
+    };
+    pub const mat2 = struct {
+        pub const P2_6 = 5;
+        pub const P3_12 = 4;
+        pub const P1_4 = 4;
+    };
+    pub const mat3 = struct {
+        pub const P2_7 = 5;
+        pub const P3_13 = 4;
+        pub const P1_5 = 4;
+    };
+};
+
+pub const CTIMER2 = struct {
+    pub const mat0 = struct {
+        pub const P1_10 = 4;
+        pub const P2_0 = 5;
+        pub const P2_20 = 4;
+        pub const P3_18 = 4;
+    };
+    pub const mat1 = struct {
+        pub const P1_11 = 4;
+        pub const P2_1 = 5;
+        pub const P2_21 = 4;
+        pub const P3_19 = 4;
+    };
+    pub const mat2 = struct {
+        pub const P1_12 = 4;
+        pub const P2_2 = 5;
+        pub const P3_20 = 4;
+    };
+    pub const mat3 = struct {
+        pub const P1_13 = 4;
+        pub const P2_3 = 5;
+        pub const P2_23 = 4;
+        pub const P3_21 = 4;
+    };
+};
+
+pub const CTIMER3 = struct {
+    pub const mat0 = struct {
+        pub const P1_14 = 5;
+        pub const P2_16 = 4;
+    };
+    pub const mat1 = struct {
+        pub const P1_15 = 5;
+        pub const P2_17 = 4;
+        pub const P3_27 = 5;
+    };
+    pub const mat2 = struct {
+        pub const P2_10 = 4;
+        pub const P3_28 = 5;
+    };
+    pub const mat3 = struct {
+        pub const P2_11 = 4;
+        pub const P2_19 = 4;
+        pub const P3_29 = 5;
+    };
+};
+
+pub const CTIMER4 = struct {
+    pub const mat0 = struct {
+        pub const P4_2 = 4;
+        pub const P2_12 = 4;
+        pub const P3_2 = 4;
+        pub const P1_6 = 5;
+    };
+    pub const mat1 = struct {
+        pub const P4_3 = 4;
+        pub const P2_13 = 4;
+        pub const P1_7 = 5;
+    };
+    pub const mat2 = struct {
+        pub const P4_4 = 4;
+        pub const P3_6 = 4;
+    };
+    pub const mat3 = struct {
+        pub const P4_5 = 4;
+        pub const P2_15 = 4;
+        pub const P3_7 = 4;
+    };
+};
+
+pub const DAC0 = struct {
+    pub const out = struct {
+        pub const P2_2 = 0;
+    };
+};
+
+pub const FLEXIO0 = struct {
+    pub const d0 = struct {
+        pub const P0_0 = 6;
+        pub const P0_16 = 6;
+    };
+    pub const d1 = struct {
+        pub const P0_1 = 6;
+        pub const P0_17 = 6;
+    };
+    pub const d10 = struct {
+        pub const P4_2 = 6;
+        pub const P2_2 = 6;
+        pub const P3_2 = 6;
+        pub const P1_2 = 6;
+    };
+    pub const d11 = struct {
+        pub const P4_3 = 6;
+        pub const P2_3 = 6;
+        pub const P1_3 = 6;
+    };
+    pub const d12 = struct {
+        pub const P4_4 = 6;
+        pub const P2_4 = 6;
+        pub const P1_4 = 6;
+    };
+    pub const d13 = struct {
+        pub const P4_5 = 6;
+        pub const P2_5 = 6;
+        pub const P1_5 = 6;
+    };
+    pub const d14 = struct {
+        pub const P4_6 = 6;
+        pub const P2_6 = 6;
+        pub const P3_6 = 6;
+        pub const P1_6 = 6;
+    };
+    pub const d15 = struct {
+        pub const P4_7 = 6;
+        pub const P2_7 = 6;
+        pub const P3_7 = 6;
+        pub const P1_7 = 6;
+    };
+    pub const d16 = struct {
+        pub const P1_8 = 6;
+        pub const P3_8 = 6;
+    };
+    pub const d17 = struct {
+        pub const P1_9 = 6;
+        pub const P3_9 = 6;
+    };
+    pub const d18 = struct {
+        pub const P1_10 = 6;
+        pub const P2_10 = 6;
+        pub const P3_10 = 6;
+    };
+    pub const d19 = struct {
+        pub const P1_11 = 6;
+        pub const P2_11 = 6;
+        pub const P3_11 = 6;
+    };
+    pub const d2 = struct {
+        pub const P0_2 = 6;
+        pub const P0_18 = 6;
+    };
+    pub const d20 = struct {
+        pub const P1_12 = 6;
+        pub const P2_12 = 6;
+        pub const P3_12 = 6;
+    };
+    pub const d21 = struct {
+        pub const P1_13 = 6;
+        pub const P2_13 = 6;
+        pub const P3_13 = 6;
+    };
+    pub const d22 = struct {
+        pub const P1_14 = 6;
+        pub const P3_14 = 6;
+    };
+    pub const d23 = struct {
+        pub const P1_15 = 6;
+        pub const P2_15 = 6;
+        pub const P3_15 = 6;
+    };
+    pub const d24 = struct {
+        pub const P2_16 = 6;
+        pub const P3_16 = 6;
+    };
+    pub const d25 = struct {
+        pub const P2_17 = 6;
+        pub const P3_17 = 6;
+    };
+    pub const d26 = struct {
+        pub const P3_18 = 6;
+    };
+    pub const d27 = struct {
+        pub const P2_19 = 6;
+        pub const P3_27 = 6;
+        pub const P3_19 = 6;
+    };
+    pub const d28 = struct {
+        pub const P2_20 = 6;
+        pub const P3_28 = 6;
+        pub const P3_20 = 6;
+    };
+    pub const d29 = struct {
+        pub const P2_21 = 6;
+        pub const P3_29 = 6;
+        pub const P3_21 = 6;
+    };
+    pub const d3 = struct {
+        pub const P0_3 = 6;
+        pub const P0_19 = 6;
+    };
+    pub const d30 = struct {
+        pub const P1_30 = 6;
+        pub const P3_30 = 6;
+        pub const P3_22 = 6;
+    };
+    pub const d31 = struct {
+        pub const P1_31 = 6;
+        pub const P2_23 = 6;
+        pub const P3_31 = 6;
+    };
+    pub const d4 = struct {
+        pub const P0_20 = 6;
+    };
+    pub const d5 = struct {
+        pub const P0_21 = 6;
+    };
+    pub const d6 = struct {
+        pub const P0_6 = 6;
+        pub const P0_22 = 6;
+    };
+    pub const d7 = struct {
+        pub const P0_23 = 6;
+    };
+    pub const d8 = struct {
+        pub const P2_0 = 6;
+        pub const P3_0 = 6;
+        pub const P1_0 = 6;
+    };
+    pub const d9 = struct {
+        pub const P2_1 = 6;
+        pub const P3_1 = 6;
+        pub const P1_1 = 6;
+    };
+};
+
+pub const I3C0 = struct {
+    pub const pur = struct {
+        pub const P1_11 = 10;
+        pub const P0_2 = 10;
+    };
+    pub const scl = struct {
+        pub const P1_9 = 10;
+        pub const P1_31 = 10;
+        pub const P0_17 = 10;
+    };
+    pub const sda = struct {
+        pub const P1_8 = 10;
+        pub const P1_30 = 10;
+        pub const P0_16 = 10;
+    };
+};
+
+pub const LPI2C0 = struct {
+    pub const hreq = struct {
+        pub const P0_6 = 2;
+    };
+    pub const scl = struct {
+        pub const P1_31 = 3;
+        pub const P0_17 = 2;
+    };
+    pub const scls = struct {
+        pub const P0_18 = 2;
+    };
+    pub const sda = struct {
+        pub const P1_30 = 3;
+        pub const P0_16 = 2;
+    };
+    pub const sdas = struct {
+        pub const P0_19 = 2;
+    };
+};
+
+pub const LPI2C1 = struct {
+    pub const scl = struct {
+        pub const P1_13 = 2;
+        pub const P1_1 = 3;
+    };
+    pub const scls = struct {
+        pub const P1_14 = 2;
+        pub const P1_3 = 3;
+    };
+    pub const sda = struct {
+        pub const P1_12 = 2;
+        pub const P1_0 = 3;
+    };
+    pub const sdas = struct {
+        pub const P1_15 = 2;
+        pub const P1_2 = 3;
+    };
+};
+
+pub const LPI2C2 = struct {
+    pub const hreq = struct {
+        pub const P4_6 = 2;
+    };
+    pub const scl = struct {
+        pub const P1_9 = 3;
+        pub const P4_3 = 2;
+    };
+    pub const scls = struct {
+        pub const P1_11 = 3;
+        pub const P4_5 = 2;
+    };
+    pub const sda = struct {
+        pub const P1_8 = 3;
+        pub const P4_4 = 2;
+    };
+    pub const sdas = struct {
+        pub const P1_10 = 3;
+        pub const P4_2 = 2;
+    };
+};
+
+pub const LPI2C3 = struct {
+    pub const hreq = struct {
+        pub const P3_29 = 2;
+    };
+    pub const scl = struct {
+        pub const P3_27 = 2;
+        pub const P3_21 = 2;
+    };
+    pub const scls = struct {
+        pub const P3_30 = 2;
+    };
+    pub const sda = struct {
+        pub const P3_28 = 2;
+        pub const P3_20 = 2;
+    };
+    pub const sdas = struct {
+        pub const P3_31 = 2;
+    };
+};
+
+pub const LPSPI0 = struct {
+    pub const pcs0 = struct {
+        pub const P0_0 = 3;
+        pub const P1_3 = 2;
+    };
+    pub const pcs1 = struct {
+        pub const P0_6 = 3;
+        pub const P1_6 = 2;
+    };
+    pub const pcs2 = struct {
+        pub const P0_16 = 3;
+        pub const P1_5 = 2;
+    };
+    pub const pcs3 = struct {
+        pub const P0_17 = 3;
+        pub const P1_4 = 2;
+    };
+    pub const sck = struct {
+        pub const P0_2 = 3;
+        pub const P1_1 = 2;
+    };
+    pub const sdi = struct {
+        pub const P0_1 = 3;
+        pub const P1_2 = 2;
+    };
+    pub const sdo = struct {
+        pub const P0_3 = 3;
+        pub const P1_0 = 2;
+    };
+};
+
+pub const LPSPI1 = struct {
+    pub const pcs0 = struct {
+        pub const P2_17 = 2;
+        pub const P3_11 = 2;
+    };
+    pub const pcs1 = struct {
+        pub const P2_6 = 2;
+        pub const P3_2 = 2;
+    };
+    pub const pcs2 = struct {
+        pub const P2_20 = 2;
+        pub const P3_7 = 2;
+    };
+    pub const pcs3 = struct {
+        pub const P2_21 = 2;
+        pub const P3_6 = 2;
+    };
+    pub const sck = struct {
+        pub const P2_12 = 2;
+        pub const P3_10 = 2;
+    };
+    pub const sdi = struct {
+        pub const P2_15 = 2;
+        pub const P2_16 = 2;
+        pub const P3_9 = 2;
+    };
+    pub const sdo = struct {
+        pub const P2_13 = 2;
+        pub const P3_8 = 2;
+    };
+};
+
+pub const LPUART0 = struct {
+    pub const cts = struct {
+        pub const P2_3 = 2;
+        pub const P0_1 = 2;
+        pub const P0_23 = 3;
+    };
+    pub const rts = struct {
+        pub const P2_2 = 2;
+        pub const P0_0 = 2;
+        pub const P0_22 = 3;
+    };
+    pub const rxd = struct {
+        pub const P2_0 = 2;
+        pub const P0_2 = 2;
+        pub const P0_20 = 3;
+    };
+    pub const txd = struct {
+        pub const P2_1 = 2;
+        pub const P0_3 = 2;
+        pub const P0_21 = 3;
+    };
+};
+
+pub const LPUART1 = struct {
+    pub const cts = struct {
+        pub const P1_11 = 2;
+        pub const P2_17 = 3;
+        pub const P3_11 = 3;
+    };
+    pub const rts = struct {
+        pub const P1_10 = 2;
+        pub const P2_15 = 3;
+        pub const P2_16 = 3;
+        pub const P3_22 = 3;
+        pub const P3_10 = 3;
+    };
+    pub const rxd = struct {
+        pub const P1_8 = 2;
+        pub const P2_12 = 3;
+        pub const P3_20 = 3;
+        pub const P3_8 = 3;
+    };
+    pub const txd = struct {
+        pub const P1_9 = 2;
+        pub const P2_13 = 3;
+        pub const P3_21 = 3;
+        pub const P3_9 = 3;
+    };
+};
+
+pub const LPUART2 = struct {
+    pub const cts = struct {
+        pub const P1_15 = 3;
+        pub const P2_4 = 3;
+        pub const P3_13 = 2;
+        pub const P1_7 = 3;
+    };
+    pub const rts = struct {
+        pub const P1_14 = 3;
+        pub const P2_5 = 3;
+        pub const P3_12 = 2;
+        pub const P1_6 = 3;
+    };
+    pub const rxd = struct {
+        pub const P1_12 = 3;
+        pub const P2_3 = 3;
+        pub const P2_11 = 3;
+        pub const P3_14 = 2;
+        pub const P1_4 = 3;
+    };
+    pub const txd = struct {
+        pub const P1_13 = 3;
+        pub const P2_2 = 3;
+        pub const P2_10 = 3;
+        pub const P3_15 = 2;
+        pub const P1_5 = 3;
+    };
+};
+
+pub const LPUART3 = struct {
+    pub const cts = struct {
+        pub const P4_6 = 3;
+        pub const P3_14 = 3;
+        pub const P3_7 = 3;
+    };
+    pub const rts = struct {
+        pub const P4_7 = 3;
+        pub const P3_15 = 3;
+        pub const P3_6 = 3;
+    };
+    pub const rxd = struct {
+        pub const P4_2 = 3;
+        pub const P3_13 = 3;
+        pub const P3_0 = 3;
+    };
+    pub const txd = struct {
+        pub const P4_5 = 3;
+        pub const P3_12 = 3;
+        pub const P3_1 = 3;
+    };
+};
+
+pub const LPUART4 = struct {
+    pub const cts = struct {
+        pub const P2_0 = 3;
+        pub const P3_31 = 3;
+        pub const P3_17 = 2;
+    };
+    pub const rts = struct {
+        pub const P2_1 = 3;
+        pub const P3_30 = 3;
+        pub const P3_16 = 2;
+    };
+    pub const rxd = struct {
+        pub const P4_4 = 3;
+        pub const P2_6 = 3;
+        pub const P3_28 = 3;
+        pub const P3_18 = 2;
+    };
+    pub const txd = struct {
+        pub const P4_3 = 3;
+        pub const P2_7 = 3;
+        pub const P3_27 = 3;
+        pub const P3_19 = 2;
+    };
+};
+
+pub const OPAMP0 = struct {
+    pub const inn = struct {
+        pub const P2_13 = 0;
+    };
+    pub const inp0 = struct {
+        pub const P2_12 = 0;
+    };
+    pub const out = struct {
+        pub const P2_15 = 0;
+    };
+};
+
+pub const RESET = struct {
+    pub const btn = struct {
+        pub const P1_29 = 1;
+    };
+};
+
+pub const TRIG = struct {
+    pub const in0 = struct {
+        pub const P3_0 = 1;
+        pub const P1_0 = 1;
+    };
+    pub const in1 = struct {
+        pub const P3_1 = 1;
+        pub const P1_1 = 1;
+    };
+    pub const in10 = struct {
+        pub const P3_31 = 1;
+    };
+    pub const in11 = struct {
+        pub const P3_28 = 1;
+    };
+    pub const in2 = struct {
+        pub const P3_7 = 1;
+        pub const P1_6 = 1;
+    };
+    pub const in3 = struct {
+        pub const P1_13 = 1;
+        pub const P3_8 = 1;
+    };
+    pub const in4 = struct {
+        pub const P1_31 = 1;
+        pub const P4_6 = 1;
+        pub const P2_11 = 1;
+        pub const P3_9 = 1;
+    };
+    pub const in5 = struct {
+        pub const P4_7 = 1;
+        pub const P2_7 = 1;
+        pub const P3_10 = 1;
+    };
+    pub const in6 = struct {
+        pub const P2_0 = 1;
+        pub const P2_2 = 1;
+        pub const P3_11 = 1;
+    };
+    pub const in7 = struct {
+        pub const P2_1 = 1;
+        pub const P2_3 = 1;
+    };
+    pub const in8 = struct {
+        pub const P2_13 = 1;
+        pub const P2_20 = 1;
+    };
+    pub const in9 = struct {
+        pub const P2_17 = 1;
+        pub const P2_21 = 1;
+    };
+    pub const out0 = struct {
+        pub const P3_20 = 1;
+        pub const P1_2 = 1;
+    };
+    pub const out1 = struct {
+        pub const P3_21 = 1;
+        pub const P1_3 = 1;
+    };
+    pub const out2 = struct {
+        pub const P1_11 = 1;
+        pub const P1_7 = 1;
+    };
+    pub const out3 = struct {
+        pub const P1_30 = 1;
+        pub const P4_5 = 1;
+    };
+    pub const out4 = struct {
+        pub const P2_6 = 1;
+        pub const P2_15 = 1;
+    };
+    pub const out5 = struct {
+        pub const P2_10 = 1;
+        pub const P2_19 = 1;
+        pub const P2_23 = 1;
+    };
+    pub const out6 = struct {
+        pub const P3_30 = 1;
+    };
+    pub const out7 = struct {
+        pub const P3_27 = 1;
+    };
+};
+
+pub const USB0 = struct {
+    pub const det = struct {
+        pub const P2_12 = 1;
+    };
+};
+
+pub const P0_0 = enum(u4) {
+    FLEXIO0_d0 = 6,
+    LPSPI0_pcs0 = 3,
+    LPUART0_rts = 2,
+    CT_inp0 = 4,
+};
+
+pub const P0_1 = enum(u4) {
+    FLEXIO0_d1 = 6,
+    LPSPI0_sdi = 3,
+    LPUART0_cts = 2,
+    CT_inp1 = 4,
+};
+
+pub const P0_16 = enum(u4) {
+    I3C0_sda = 10,
+    CTIMER0_mat0 = 4,
+    FLEXIO0_d0 = 6,
+    LPI2C0_sda = 2,
+    LPSPI0_pcs2 = 3,
+};
+
+pub const P0_17 = enum(u4) {
+    I3C0_scl = 10,
+    CTIMER0_mat1 = 4,
+    FLEXIO0_d1 = 6,
+    LPI2C0_scl = 2,
+    LPSPI0_pcs3 = 3,
+};
+
+pub const P0_18 = enum(u4) {
+    CTIMER0_mat2 = 4,
+    FLEXIO0_d2 = 6,
+    LPI2C0_scls = 2,
+    ADC0_a8 = 0,
+    CMP0_out = 8,
+};
+
+pub const P0_19 = enum(u4) {
+    CTIMER0_mat3 = 4,
+    FLEXIO0_d3 = 6,
+    LPI2C0_sdas = 2,
+    ADC0_a9 = 0,
+    CMP1_out = 8,
+};
+
+pub const P0_2 = enum(u4) {
+    I3C0_pur = 10,
+    CTIMER0_mat0 = 4,
+    FLEXIO0_d2 = 6,
+    LPSPI0_sck = 3,
+    LPUART0_rxd = 2,
+};
+
+pub const P0_20 = enum(u4) {
+    FLEXIO0_d4 = 6,
+    LPUART0_rxd = 3,
+    ADC0_a10 = 0,
+    CT_inp0 = 4,
+};
+
+pub const P0_21 = enum(u4) {
+    FLEXIO0_d5 = 6,
+    LPUART0_txd = 3,
+    ADC0_a11 = 0,
+    CT_inp1 = 4,
+};
+
+pub const P0_22 = enum(u4) {
+    CTIMER0_mat0 = 5,
+    FLEXIO0_d6 = 6,
+    LPUART0_rts = 3,
+    ADC0_a12 = 0,
+    CT_inp2 = 4,
+};
+
+pub const P0_23 = enum(u4) {
+    CTIMER0_mat1 = 5,
+    FLEXIO0_d7 = 6,
+    LPUART0_cts = 3,
+    ADC0_a13 = 0,
+    CT_inp3 = 4,
+};
+
+pub const P0_3 = enum(u4) {
+    CTIMER0_mat1 = 4,
+    FLEXIO0_d3 = 6,
+    LPSPI0_sdo = 3,
+    LPUART0_txd = 2,
+    ADC0_a14 = 0,
+    CMP0_out = 8,
+    CMP1_in1 = 0,
+};
+
+pub const P0_6 = enum(u4) {
+    FLEXIO0_d6 = 6,
+    LPI2C0_hreq = 2,
+    LPSPI0_pcs1 = 3,
+    ADC0_a15 = 0,
+    CMP1_out = 8,
+    CLKOUT_clkout = 12,
+    CT_inp2 = 4,
+};
+
+pub const P1_0 = enum(u4) {
+    TRIG_in0 = 1,
+    CTIMER0_mat2 = 5,
+    FLEXIO0_d8 = 6,
+    LPI2C1_sda = 3,
+    LPSPI0_sdo = 2,
+    ADC0_a16 = 0,
+    CMP0_in3 = 0,
+    CT_inp4 = 4,
+};
+
+pub const P1_1 = enum(u4) {
+    TRIG_in1 = 1,
+    CTIMER0_mat3 = 5,
+    FLEXIO0_d9 = 6,
+    LPI2C1_scl = 3,
+    LPSPI0_sck = 2,
+    ADC0_a17 = 0,
+    CMP1_in3 = 0,
+    CT_inp5 = 4,
+};
+
+pub const P1_10 = enum(u4) {
+    CTIMER2_mat0 = 4,
+    FLEXIO0_d18 = 6,
+    LPI2C2_sdas = 3,
+    LPUART1_rts = 2,
+    ADC1_a8 = 0,
+    CAN0_txd = 11,
+};
+
+pub const P1_11 = enum(u4) {
+    TRIG_out2 = 1,
+    I3C0_pur = 10,
+    CTIMER2_mat1 = 4,
+    FLEXIO0_d19 = 6,
+    LPI2C2_scls = 3,
+    LPUART1_cts = 2,
+    ADC1_a9 = 0,
+    CAN0_rxd = 11,
+};
+
+pub const P1_12 = enum(u4) {
+    CTIMER2_mat2 = 4,
+    FLEXIO0_d20 = 6,
+    LPI2C1_sda = 2,
+    LPUART2_rxd = 3,
+    ADC1_a10 = 0,
+    CAN0_rxd = 11,
+};
+
+pub const P1_13 = enum(u4) {
+    TRIG_in3 = 1,
+    CTIMER2_mat3 = 4,
+    FLEXIO0_d21 = 6,
+    LPI2C1_scl = 2,
+    LPUART2_txd = 3,
+    ADC1_a11 = 0,
+    CAN0_txd = 11,
+};
+
+pub const P1_14 = enum(u4) {
+    CTIMER3_mat0 = 5,
+    FLEXIO0_d22 = 6,
+    LPI2C1_scls = 2,
+    LPUART2_rts = 3,
+    ADC1_a12 = 0,
+    CT_inp10 = 4,
+};
+
+pub const P1_15 = enum(u4) {
+    CTIMER3_mat1 = 5,
+    FLEXIO0_d23 = 6,
+    LPI2C1_sdas = 2,
+    LPUART2_cts = 3,
+    ADC1_a13 = 0,
+    CT_inp11 = 4,
+};
+
+pub const P1_2 = enum(u4) {
+    TRIG_out0 = 1,
+    CTIMER1_mat0 = 4,
+    FLEXIO0_d10 = 6,
+    LPI2C1_sdas = 3,
+    LPSPI0_sdi = 2,
+    ADC0_a18 = 0,
+    CAN0_txd = 11,
+    CT_inp0 = 5,
+};
+
+pub const P1_29 = enum(u4) {
+    RESET_btn = 1,
+};
+
+pub const P1_3 = enum(u4) {
+    TRIG_out1 = 1,
+    CTIMER1_mat1 = 4,
+    FLEXIO0_d11 = 6,
+    LPI2C1_scls = 3,
+    LPSPI0_pcs0 = 2,
+    ADC0_a19 = 0,
+    CMP0_in1 = 0,
+    CAN0_rxd = 11,
+    CT_inp1 = 5,
+};
+
+pub const P1_30 = enum(u4) {
+    TRIG_out3 = 1,
+    I3C0_sda = 10,
+    FLEXIO0_d30 = 6,
+    LPI2C0_sda = 3,
+    CT_inp16 = 4,
+};
+
+pub const P1_31 = enum(u4) {
+    TRIG_in4 = 1,
+    I3C0_scl = 10,
+    FLEXIO0_d31 = 6,
+    LPI2C0_scl = 3,
+    CT_inp17 = 4,
+};
+
+pub const P1_4 = enum(u4) {
+    CTIMER1_mat2 = 4,
+    FLEXIO0_d12 = 6,
+    LPSPI0_pcs3 = 2,
+    LPUART2_rxd = 3,
+    ADC0_a20 = 0,
+    CMP0_in2 = 0,
+};
+
+pub const P1_5 = enum(u4) {
+    CTIMER1_mat3 = 4,
+    FLEXIO0_d13 = 6,
+    LPSPI0_pcs2 = 2,
+    LPUART2_txd = 3,
+    ADC0_a21 = 0,
+    CMP1_in2 = 0,
+};
+
+pub const P1_6 = enum(u4) {
+    TRIG_in2 = 1,
+    CTIMER4_mat0 = 5,
+    FLEXIO0_d14 = 6,
+    LPSPI0_pcs1 = 2,
+    LPUART2_rts = 3,
+    ADC0_a22 = 0,
+    CAN0_txd = 11,
+    CT_inp6 = 4,
+};
+
+pub const P1_7 = enum(u4) {
+    TRIG_out2 = 1,
+    CTIMER4_mat1 = 5,
+    FLEXIO0_d15 = 6,
+    LPUART2_cts = 3,
+    ADC0_a23 = 0,
+    CAN0_rxd = 11,
+    CT_inp7 = 4,
+};
+
+pub const P1_8 = enum(u4) {
+    I3C0_sda = 10,
+    CTIMER0_mat2 = 5,
+    FLEXIO0_d16 = 6,
+    LPI2C2_sda = 3,
+    LPUART1_rxd = 2,
+    CT_inp8 = 4,
+};
+
+pub const P1_9 = enum(u4) {
+    I3C0_scl = 10,
+    CTIMER0_mat3 = 5,
+    FLEXIO0_d17 = 6,
+    LPI2C2_scl = 3,
+    LPUART1_txd = 2,
+    CT_inp9 = 4,
+};
+
+pub const P2_0 = enum(u4) {
+    TRIG_in6 = 1,
+    CTIMER2_mat0 = 5,
+    FLEXIO0_d8 = 6,
+    LPUART0_rxd = 2,
+    LPUART4_cts = 3,
+    ADC0_a0 = 0,
+    CT_inp16 = 4,
+};
+
+pub const P2_1 = enum(u4) {
+    TRIG_in7 = 1,
+    CTIMER2_mat1 = 5,
+    FLEXIO0_d9 = 6,
+    LPUART0_txd = 2,
+    LPUART4_rts = 3,
+    ADC0_a1 = 0,
+    CT_inp17 = 4,
+};
+
+pub const P2_10 = enum(u4) {
+    TRIG_out5 = 1,
+    CTIMER3_mat2 = 4,
+    FLEXIO0_d18 = 6,
+    LPUART2_txd = 3,
+};
+
+pub const P2_11 = enum(u4) {
+    TRIG_in4 = 1,
+    CTIMER3_mat3 = 4,
+    FLEXIO0_d19 = 6,
+    LPUART2_rxd = 3,
+};
+
+pub const P2_12 = enum(u4) {
+    CTIMER0_mat0 = 5,
+    CTIMER4_mat0 = 4,
+    FLEXIO0_d20 = 6,
+    LPSPI1_sck = 2,
+    LPUART1_rxd = 3,
+    USB0_det = 1,
+    ADC0_a5 = 0,
+    OPAMP0_inp0 = 0,
+    CAN0_rxd = 11,
+};
+
+pub const P2_13 = enum(u4) {
+    TRIG_in8 = 1,
+    CTIMER0_mat1 = 5,
+    CTIMER4_mat1 = 4,
+    FLEXIO0_d21 = 6,
+    LPSPI1_sdo = 2,
+    LPUART1_txd = 3,
+    ADC1_a5 = 0,
+    OPAMP0_inn = 0,
+    CAN0_txd = 11,
+};
+
+pub const P2_15 = enum(u4) {
+    TRIG_out4 = 1,
+    CTIMER0_mat2 = 5,
+    CTIMER4_mat3 = 4,
+    FLEXIO0_d23 = 6,
+    LPSPI1_sdi = 2,
+    LPUART1_rts = 3,
+    ADC0_a2 = 0,
+    OPAMP0_out = 0,
+};
+
+pub const P2_16 = enum(u4) {
+    CTIMER0_mat2 = 5,
+    CTIMER3_mat0 = 4,
+    FLEXIO0_d24 = 6,
+    LPSPI1_sdi = 2,
+    LPUART1_rts = 3,
+    ADC0_a6 = 0,
+};
+
+pub const P2_17 = enum(u4) {
+    TRIG_in9 = 1,
+    CTIMER0_mat3 = 5,
+    CTIMER3_mat1 = 4,
+    FLEXIO0_d25 = 6,
+    LPSPI1_pcs0 = 2,
+    LPUART1_cts = 3,
+    ADC1_a6 = 0,
+};
+
+pub const P2_19 = enum(u4) {
+    TRIG_out5 = 1,
+    CTIMER3_mat3 = 4,
+    FLEXIO0_d27 = 6,
+    ADC1_a2 = 0,
+};
+
+pub const P2_2 = enum(u4) {
+    TRIG_in6 = 1,
+    CTIMER2_mat2 = 5,
+    FLEXIO0_d10 = 6,
+    LPUART0_rts = 2,
+    LPUART2_txd = 3,
+    ADC0_a4 = 0,
+    CMP0_in0 = 0,
+    DAC0_out = 0,
+    CT_inp12 = 4,
+};
+
+pub const P2_20 = enum(u4) {
+    TRIG_in8 = 1,
+    CTIMER2_mat0 = 4,
+    FLEXIO0_d28 = 6,
+    LPSPI1_pcs2 = 2,
+};
+
+pub const P2_21 = enum(u4) {
+    TRIG_in9 = 1,
+    CTIMER2_mat1 = 4,
+    FLEXIO0_d29 = 6,
+    LPSPI1_pcs3 = 2,
+};
+
+pub const P2_23 = enum(u4) {
+    TRIG_out5 = 1,
+    CTIMER2_mat3 = 4,
+    FLEXIO0_d31 = 6,
+};
+
+pub const P2_3 = enum(u4) {
+    TRIG_in7 = 1,
+    CTIMER2_mat3 = 5,
+    FLEXIO0_d11 = 6,
+    LPUART0_cts = 2,
+    LPUART2_rxd = 3,
+    ADC1_a4 = 0,
+    CMP1_in0 = 0,
+    CT_inp13 = 4,
+};
+
+pub const P2_4 = enum(u4) {
+    CTIMER1_mat0 = 5,
+    FLEXIO0_d12 = 6,
+    LPUART2_cts = 3,
+    ADC1_a0 = 0,
+    CT_inp14 = 4,
+};
+
+pub const P2_5 = enum(u4) {
+    CTIMER1_mat1 = 5,
+    FLEXIO0_d13 = 6,
+    LPUART2_rts = 3,
+    ADC1_a1 = 0,
+    CT_inp15 = 4,
+};
+
+pub const P2_6 = enum(u4) {
+    TRIG_out4 = 1,
+    CTIMER1_mat2 = 5,
+    FLEXIO0_d14 = 6,
+    LPSPI1_pcs1 = 2,
+    LPUART4_rxd = 3,
+    ADC1_a3 = 0,
+    CT_inp18 = 4,
+};
+
+pub const P2_7 = enum(u4) {
+    TRIG_in5 = 1,
+    CTIMER1_mat3 = 5,
+    FLEXIO0_d15 = 6,
+    LPUART4_txd = 3,
+    ADC0_a7 = 0,
+    ADC1_a7 = 0,
+    CT_inp19 = 4,
+};
+
+pub const P3_0 = enum(u4) {
+    TRIG_in0 = 1,
+    FLEXIO0_d8 = 6,
+    LPUART3_rxd = 3,
+    CT_inp16 = 4,
+};
+
+pub const P3_1 = enum(u4) {
+    TRIG_in1 = 1,
+    FLEXIO0_d9 = 6,
+    LPUART3_txd = 3,
+    CT_inp17 = 4,
+};
+
+pub const P3_10 = enum(u4) {
+    TRIG_in5 = 1,
+    CTIMER1_mat0 = 4,
+    FLEXIO0_d18 = 6,
+    LPSPI1_sck = 2,
+    LPUART1_rts = 3,
+};
+
+pub const P3_11 = enum(u4) {
+    TRIG_in6 = 1,
+    CTIMER1_mat1 = 4,
+    FLEXIO0_d19 = 6,
+    LPSPI1_pcs0 = 2,
+    LPUART1_cts = 3,
+};
+
+pub const P3_12 = enum(u4) {
+    CTIMER1_mat2 = 4,
+    FLEXIO0_d20 = 6,
+    LPUART2_rts = 2,
+    LPUART3_txd = 3,
+};
+
+pub const P3_13 = enum(u4) {
+    CTIMER1_mat3 = 4,
+    FLEXIO0_d21 = 6,
+    LPUART2_cts = 2,
+    LPUART3_rxd = 3,
+};
+
+pub const P3_14 = enum(u4) {
+    FLEXIO0_d22 = 6,
+    LPUART2_rxd = 2,
+    LPUART3_cts = 3,
+    CT_inp6 = 4,
+};
+
+pub const P3_15 = enum(u4) {
+    FLEXIO0_d23 = 6,
+    LPUART2_txd = 2,
+    LPUART3_rts = 3,
+    CT_inp7 = 4,
+};
+
+pub const P3_16 = enum(u4) {
+    FLEXIO0_d24 = 6,
+    LPUART4_rts = 2,
+    CT_inp8 = 4,
+};
+
+pub const P3_17 = enum(u4) {
+    FLEXIO0_d25 = 6,
+    LPUART4_cts = 2,
+    CT_inp9 = 4,
+};
+
+pub const P3_18 = enum(u4) {
+    CTIMER2_mat0 = 4,
+    FLEXIO0_d26 = 6,
+    LPUART4_rxd = 2,
+};
+
+pub const P3_19 = enum(u4) {
+    CTIMER2_mat1 = 4,
+    FLEXIO0_d27 = 6,
+    LPUART4_txd = 2,
+};
+
+pub const P3_2 = enum(u4) {
+    CTIMER4_mat0 = 4,
+    FLEXIO0_d10 = 6,
+    LPSPI1_pcs1 = 2,
+};
+
+pub const P3_20 = enum(u4) {
+    TRIG_out0 = 1,
+    CTIMER2_mat2 = 4,
+    FLEXIO0_d28 = 6,
+    LPI2C3_sda = 2,
+    LPUART1_rxd = 3,
+};
+
+pub const P3_21 = enum(u4) {
+    TRIG_out1 = 1,
+    CTIMER2_mat3 = 4,
+    FLEXIO0_d29 = 6,
+    LPI2C3_scl = 2,
+    LPUART1_txd = 3,
+};
+
+pub const P3_22 = enum(u4) {
+    FLEXIO0_d30 = 6,
+    LPUART1_rts = 3,
+    CT_inp10 = 4,
+};
+
+pub const P3_27 = enum(u4) {
+    TRIG_out7 = 1,
+    CTIMER3_mat1 = 5,
+    FLEXIO0_d27 = 6,
+    LPI2C3_scl = 2,
+    LPUART4_txd = 3,
+    CT_inp13 = 4,
+};
+
+pub const P3_28 = enum(u4) {
+    TRIG_in11 = 1,
+    CTIMER3_mat2 = 5,
+    FLEXIO0_d28 = 6,
+    LPI2C3_sda = 2,
+    LPUART4_rxd = 3,
+    CT_inp12 = 4,
+};
+
+pub const P3_29 = enum(u4) {
+    CTIMER3_mat3 = 5,
+    FLEXIO0_d29 = 6,
+    LPI2C3_hreq = 2,
+    ADC1_a22 = 0,
+    CT_inp3 = 4,
+};
+
+pub const P3_30 = enum(u4) {
+    TRIG_out6 = 1,
+    CTIMER0_mat2 = 4,
+    FLEXIO0_d30 = 6,
+    LPI2C3_scls = 2,
+    LPUART4_rts = 3,
+    ADC1_a21 = 0,
+};
+
+pub const P3_31 = enum(u4) {
+    TRIG_in10 = 1,
+    CTIMER0_mat3 = 4,
+    FLEXIO0_d31 = 6,
+    LPI2C3_sdas = 2,
+    LPUART4_cts = 3,
+    ADC1_a20 = 0,
+};
+
+pub const P3_6 = enum(u4) {
+    CTIMER4_mat2 = 4,
+    FLEXIO0_d14 = 6,
+    LPSPI1_pcs3 = 2,
+    LPUART3_rts = 3,
+    CLKOUT_clkout = 1,
+};
+
+pub const P3_7 = enum(u4) {
+    TRIG_in2 = 1,
+    CTIMER4_mat3 = 4,
+    FLEXIO0_d15 = 6,
+    LPSPI1_pcs2 = 2,
+    LPUART3_cts = 3,
+};
+
+pub const P3_8 = enum(u4) {
+    TRIG_in3 = 1,
+    FLEXIO0_d16 = 6,
+    LPSPI1_sdo = 2,
+    LPUART1_rxd = 3,
+    CLKOUT_clkout = 12,
+    CT_inp4 = 4,
+};
+
+pub const P3_9 = enum(u4) {
+    TRIG_in4 = 1,
+    FLEXIO0_d17 = 6,
+    LPSPI1_sdi = 2,
+    LPUART1_txd = 3,
+    CT_inp5 = 4,
+};
+
+pub const P4_2 = enum(u4) {
+    CTIMER4_mat0 = 4,
+    FLEXIO0_d10 = 6,
+    LPI2C2_sdas = 2,
+    LPUART3_rxd = 3,
+    CLKOUT_clkout = 1,
+};
+
+pub const P4_3 = enum(u4) {
+    CTIMER4_mat1 = 4,
+    FLEXIO0_d11 = 6,
+    LPI2C2_scl = 2,
+    LPUART4_txd = 3,
+};
+
+pub const P4_4 = enum(u4) {
+    CTIMER4_mat2 = 4,
+    FLEXIO0_d12 = 6,
+    LPI2C2_sda = 2,
+    LPUART4_rxd = 3,
+};
+
+pub const P4_5 = enum(u4) {
+    TRIG_out3 = 1,
+    CTIMER4_mat3 = 4,
+    FLEXIO0_d13 = 6,
+    LPI2C2_scls = 2,
+    LPUART3_txd = 3,
+};
+
+pub const P4_6 = enum(u4) {
+    TRIG_in4 = 1,
+    FLEXIO0_d14 = 6,
+    LPI2C2_hreq = 2,
+    LPUART3_cts = 3,
+    CT_inp6 = 4,
+};
+
+pub const P4_7 = enum(u4) {
+    TRIG_in5 = 1,
+    FLEXIO0_d15 = 6,
+    LPUART3_rts = 3,
+    CT_inp7 = 4,
+};
diff --git a/port/nxp/mcx/src/mcxa_15x/hal/meta_utils.zig b/port/nxp/mcx/src/mcxa_15x/hal/meta_utils.zig
new file mode 100644
index 000000000..9939a94e8
--- /dev/null
+++ b/port/nxp/mcx/src/mcxa_15x/hal/meta_utils.zig
@@ -0,0 +1,38 @@
+const std = @import("std");
+const mapper = @import("mapper.zig");
+
+pub fn check_mux(comptime pin: mapper.PIN, comptime sig: mapper.SIGNALS) usize {
+    const sig_pins = sig.pins();
+    const pins_mux = pin.mux();
+
+    if (@hasDecl(sig_pins, @tagName(pin))) {
+        return @field(sig_pins, @tagName(pin));
+    } else {
+        @compileError(std.fmt.comptimePrint(
+            \\Pin "{0s}" does not have a mux for "{1s}":
+            \\available Pins for "{1s}" are:
+            \\{2s}
+            \\
+            \\available Mux for Pin "{0s}" are:
+            \\{3s}
+            \\
+        , .{
+            @tagName(pin),
+            @tagName(sig),
+            list_peri_recursive(@typeInfo(sig_pins).@"struct".decl_names),
+            list_peri_recursive(@typeInfo(pins_mux).@"enum".field_names),
+        }));
+    }
+}
+
+fn list_peri_recursive(comptime names: []const []const u8) []const u8 {
+    for (names, 1..) |n, i| {
+        return " - " ++ n ++ "\n" ++ list_peri_recursive(names[i..]);
+    }
+    return "";
+}
+
+test {
+    const val = comptime check_mux(.P0_0, .LPUART0_rts);
+    @compileLog(val);
+}
diff --git a/port/nxp/mcx/src/mcxa_15x/hal/ostimer.zig b/port/nxp/mcx/src/mcxa_15x/hal/ostimer.zig
new file mode 100644
index 000000000..09a4f7387
--- /dev/null
+++ b/port/nxp/mcx/src/mcxa_15x/hal/ostimer.zig
@@ -0,0 +1,56 @@
+const microzig = @import("microzig");
+const syscon = @import("syscon.zig");
+
+const time = microzig.drivers.time;
+
+const OSTIMER0 = microzig.chip.peripherals.OSTIMER0;
+const MRCC0 = microzig.chip.peripherals.MRCC0;
+
+//TODO: allow Hal config to enable Time counting on Debug and set/clear ACC
+pub fn init() void {
+
+    //disable and reset timer
+    syscon.disable_clock(.OSTIMER0);
+    syscon.reset_assert(.OSTIMER0);
+    syscon.reset_release(.OSTIMER0);
+
+    //set clk_1m as input_clk
+    //TODO: check if FRO_12m is set in sleep mode
+
+    syscon.unlock_clock_configuration();
+    MRCC0.MRCC_OSTIMER0_CLKSEL.modify_one("MUX", @fromBackingInt(@intCast(2)));
+    syscon.freeze_clock_configuration();
+
+    syscon.enable_clock(.OSTIMER0);
+}
+
+pub fn get_time_since_boot() time.Absolute {
+    const sec = microzig.interrupt.enter_critical_section();
+    defer sec.leave();
+
+    //sev inst saves a snapshot of OSTIMER.EVCounter on OSTIMER.CAPTURE
+    microzig.cpu.sev();
+
+    //read current timer Gray value
+    var gray: u42 = OSTIMER0.CAPTURE_L.read().CAPTURE_VALUE;
+    gray |= @as(u42, OSTIMER0.CAPTURE_H.read().CAPTURE_VALUE) << 32;
+
+    //simple gray to bin convert
+    var b = gray;
+    b ^= b >> 1;
+    b ^= b >> 2;
+    b ^= b >> 4;
+    b ^= b >> 8;
+    b ^= b >> 16;
+    b ^= b >> 32;
+    return @fromBackingInt(@intCast(b));
+}
+
+pub fn sleep_ms(time_ms: u32) void {
+    sleep_us(time_ms * 1000);
+}
+
+pub fn sleep_us(time_us: u64) void {
+    const end_time = time.make_timeout_us(get_time_since_boot(), time_us);
+    while (!end_time.is_reached_by(get_time_since_boot())) {}
+}
diff --git a/port/nxp/mcx/src/mcxa_15x/hal/port.zig b/port/nxp/mcx/src/mcxa_15x/hal/port.zig
new file mode 100644
index 000000000..923282534
--- /dev/null
+++ b/port/nxp/mcx/src/mcxa_15x/hal/port.zig
@@ -0,0 +1,61 @@
+const microzig = @import("microzig");
+const syscon = @import("./syscon.zig");
+const gpio = @import("./gpio.zig");
+const mapper = @import("mapper.zig");
+
+const PORT_T = microzig.chip.types.peripherals.PORT0;
+
+//TODO ADD ALL PIN CONFG
+pub const PinConfig = struct {
+    MUX: u3,
+};
+
+const PIN_T = @FieldType(microzig.chip.types.peripherals.PORT0, "PCR0");
+
+pub fn num(comptime n: u2) Port {
+    return @fromBackingInt(n);
+}
+
+pub const Port = enum(u3) {
+    _,
+
+    pub fn init(comptime port: Port) void {
+        const tag = switch (@backingInt(port)) {
+            0 => .PORT0,
+            1 => .PORT1,
+            2 => .PORT2,
+            3 => .PORT3,
+            4 => .PORT4,
+            else => @panic("INVALID PORT"),
+        };
+
+        syscon.reset_release(tag);
+        syscon.enable_clock(tag);
+    }
+
+    pub fn get_regs(self: Port) *volatile PORT_T {
+        const val: u3 = @backingInt(self);
+
+        if (val > 4) @panic("INVALID PORT");
+
+        return switch (val) {
+            0 => microzig.chip.peripherals.PORT0,
+            1 => @ptrCast(microzig.chip.peripherals.PORT1),
+            2 => @ptrCast(microzig.chip.peripherals.PORT2),
+            3 => @ptrCast(microzig.chip.peripherals.PORT3),
+            4 => @ptrCast(microzig.chip.peripherals.PORT4),
+            else => unreachable,
+        };
+    }
+
+    pub fn configure_pin(pin: mapper.PIN, config: PinConfig) void {
+        const map = pin.map();
+        const regs = get_regs(@fromBackingInt(@intCast(map.port)));
+        const pin_regs: *volatile PIN_T = @ptrFromInt(@as(usize, @intFromPtr(regs)) + (0x80 + (4 * @as(usize, map.pin))));
+
+        pin_regs.modify_one("LK", .lk0);
+        defer pin_regs.modify_one("LK", .lk1);
+
+        pin_regs.modify_one("MUX", @fromBackingInt(@intCast(config.MUX)));
+    }
+};
diff --git a/port/nxp/mcx/src/mcxa_15x/hal/syscon.zig b/port/nxp/mcx/src/mcxa_15x/hal/syscon.zig
new file mode 100644
index 000000000..3159c9774
--- /dev/null
+++ b/port/nxp/mcx/src/mcxa_15x/hal/syscon.zig
@@ -0,0 +1,522 @@
+const microzig = @import("microzig");
+
+const chip = microzig.chip;
+
+var clocks: Clock_Frequencies = .{};
+
+pub inline fn unlock_clock_configuration() void {
+    chip.peripherals.SYSCON.CLKUNLOCK.write(.{ .UNLOCK = .ENABLE });
+}
+
+pub inline fn freeze_clock_configuration() void {
+    chip.peripherals.SYSCON.CLKUNLOCK.write(.{ .UNLOCK = .FREEZE });
+}
+
+pub fn enable_clock(comptime peripheral: Peripheral) void {
+    unlock_clock_configuration();
+    defer freeze_clock_configuration();
+
+    switch (peripheral.cc()) {
+        0 => chip.peripherals.MRCC0.MRCC_GLB_CC0_SET.write_raw(
+            @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_CC0_SET)) | peripheral.mask(),
+        ),
+        1 => chip.peripherals.MRCC0.MRCC_GLB_CC1_SET.write_raw(
+            @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_CC1_SET)) | peripheral.mask(),
+        ),
+    }
+}
+
+pub fn disable_clock(comptime peripheral: Peripheral) void {
+    unlock_clock_configuration();
+    defer freeze_clock_configuration();
+
+    switch (peripheral.cc()) {
+        0 => chip.peripherals.MRCC0.MRCC_GLB_CC0_CLR.write_raw(
+            @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_CC0_CLR)) | peripheral.mask(),
+        ),
+        1 => chip.peripherals.MRCC0.MRCC_GLB_CC1_CLR.write_raw(
+            @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_CC1_CLR)) | peripheral.mask(),
+        ),
+    }
+}
+
+pub fn reset_release(comptime peripheral: Peripheral) void {
+    unlock_clock_configuration();
+    defer freeze_clock_configuration();
+
+    switch (peripheral.cc()) {
+        0 => chip.peripherals.MRCC0.MRCC_GLB_RST0_SET.write_raw(
+            @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_RST0_SET)) | peripheral.mask(),
+        ),
+        1 => chip.peripherals.MRCC0.MRCC_GLB_RST1_SET.write_raw(
+            @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_RST1_SET)) | peripheral.mask(),
+        ),
+    }
+}
+
+pub fn reset_assert(comptime peripheral: Peripheral) void {
+    unlock_clock_configuration();
+    defer freeze_clock_configuration();
+
+    switch (peripheral.cc()) {
+        0 => chip.peripherals.MRCC0.MRCC_GLB_RST0_CLR.write_raw(
+            @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_RST0_CLR)) | peripheral.mask(),
+        ),
+        1 => chip.peripherals.MRCC0.MRCC_GLB_RST1_CLR.write_raw(
+            @as(u32, @bitCast(chip.peripherals.MRCC0.MRCC_GLB_RST1_CLR)) | peripheral.mask(),
+        ),
+    }
+}
+
+pub const Peripheral = enum {
+    // MRCC_GLB_CC0, MRCC_GLB_ACC0, MRCC_GLB_RST0
+    INPUTMUX0,
+    I3C0,
+    CTIMER0,
+    CTIMER1,
+    CTIMER2,
+    CTIMER3,
+    CTIMER4,
+    FREQME,
+    UTICK0,
+    DMA,
+    AOI0,
+    CRC0,
+    EIM0,
+    ERM0,
+    AOI1,
+    FLEXIO0,
+    LPI2C0,
+    LP12C1,
+    LPSPI0,
+    LPSPI1,
+    LPUART0,
+    LPUART1,
+    LPUART2,
+    LPUART3,
+    LPUART4,
+    USB0,
+    QDC0,
+    QDC1,
+    FLEXPWM0,
+    FLEXPWM1,
+
+    // MRCC_GLB_CC1, MRCC_GLB_ACC1, MRCC_GLB_RST1
+    OSTIMER0,
+    ADC0,
+    ADC1,
+    CMP1,
+    DAC0,
+    OPAMP0,
+
+    PORT0,
+    PORT1,
+    PORT2,
+    PORT3,
+    PORT4,
+    FLEXCAN0,
+    LPI2C2,
+    LPI2C3,
+    GPIO0,
+    GPIO1,
+    GPIO2,
+    GPIO3,
+    GPIO4,
+
+    fn cc(comptime peripheral: Peripheral) u1 {
+        return switch (peripheral) {
+            .INPUTMUX0,
+            .I3C0,
+            .CTIMER0,
+            .CTIMER1,
+            .CTIMER2,
+            .CTIMER3,
+            .CTIMER4,
+            .FREQME,
+            .UTICK0,
+            .DMA,
+            .AOI0,
+            .CRC0,
+            .EIM0,
+            .ERM0,
+            .AOI1,
+            .FLEXIO0,
+            .LPI2C0,
+            .LP12C1,
+            .LPSPI0,
+            .LPSPI1,
+            .LPUART0,
+            .LPUART1,
+            .LPUART2,
+            .LPUART3,
+            .LPUART4,
+            .USB0,
+            .QDC0,
+            .QDC1,
+            .FLEXPWM0,
+            .FLEXPWM1,
+            => 0,
+
+            .OSTIMER0,
+            .ADC0,
+            .ADC1,
+            .CMP1,
+            .DAC0,
+            .OPAMP0,
+            .PORT0,
+            .PORT1,
+            .PORT2,
+            .PORT3,
+            .PORT4,
+            .FLEXCAN0,
+            .LPI2C2,
+            .LPI2C3,
+            .GPIO0,
+            .GPIO1,
+            .GPIO2,
+            .GPIO3,
+            .GPIO4,
+            => 1,
+        };
+    }
+
+    fn mask(comptime peripheral: Peripheral) u32 {
+        return switch (peripheral) {
+            .INPUTMUX0 => 1,
+            .I3C0 => 1 << 1,
+            .CTIMER0 => 1 << 2,
+            .CTIMER1 => 1 << 3,
+            .CTIMER2 => 1 << 4,
+            .CTIMER3 => 1 << 5,
+            .CTIMER4 => 1 << 6,
+            .FREQME => 1 << 7,
+            .UTICK0 => 1 << 8,
+            .DMA => 1 << 10,
+            .AOI0 => 1 << 11,
+            .CRC0 => 1 << 12,
+            .EIM0 => 1 << 13,
+            .ERM0 => 1 << 14,
+            .AOI1 => 1 << 16,
+            .FLEXIO0 => 1 << 17,
+            .LPI2C0 => 1 << 18,
+            .LP12C1 => 1 << 19,
+            .LPSPI0 => 1 << 20,
+            .LPSPI1 => 1 << 21,
+            .LPUART0 => 1 << 22,
+            .LPUART1 => 1 << 23,
+            .LPUART2 => 1 << 24,
+            .LPUART3 => 1 << 25,
+            .LPUART4 => 1 << 26,
+            .USB0 => 1 << 27,
+            .QDC0 => 1 << 28,
+            .QDC1 => 1 << 29,
+            .FLEXPWM0 => 1 << 30,
+            .FLEXPWM1 => 1 << 31,
+            .OSTIMER0 => 1,
+            .ADC0 => 1 << 1,
+            .ADC1 => 1 << 2,
+            .CMP1 => 1 << 4,
+            .DAC0 => 1 << 5,
+            .OPAMP0 => 1 << 6,
+            .PORT0 => 1 << 7,
+            .PORT1 => 1 << 8,
+            .PORT2 => 1 << 9,
+            .PORT3 => 1 << 10,
+            .PORT4 => 1 << 11,
+            .FLEXCAN0 => 1 << 12,
+            .LPI2C2 => 1 << 13,
+            .LPI2C3 => 1 << 14,
+            .GPIO0 => 1 << 20,
+            .GPIO1 => 1 << 21,
+            .GPIO2 => 1 << 22,
+            .GPIO3 => 1 << 23,
+            .GPIO4 => 1 << 24,
+        };
+    }
+};
+
+const MRCC0 = microzig.chip.peripherals.MRCC0;
+const scg0 = microzig.chip.peripherals.SCG0;
+const spc0 = microzig.chip.peripherals.SPC0;
+const FMU = microzig.chip.peripherals.FMU0;
+const syscon = microzig.chip.peripherals.SYSCON;
+
+pub const SOSC_Range = enum(u2) {
+    @"8Mhz-16Mhz",
+    @"16Mhz-25Mhz",
+    @"25Mhz-40Mhz",
+    @"40Mhz-50Mhz",
+};
+
+///Selects the source for the external reference clock. This bit selects which clock is output from the SOSC
+///into the SCG, whether from the crystal oscillator or from an external clock input.
+pub const EREFS = enum(u1) {
+    ///reference clock selected.
+    external,
+
+    ///crystal oscillator of OSC selected.
+    internal,
+};
+
+pub const System_Clock = enum(u3) {
+    SOSC = 1,
+    SIRC,
+    FRIC,
+    ROSC,
+};
+
+pub const FIRC_FREQ = enum(u3) {
+    @"48Mhz" = 1,
+    @"64Mhz" = 3,
+    @"96Mhz" = 5,
+    @"192Mhz" = 7,
+};
+
+pub const Drive_Mode = enum(u2) {
+    MidDriver = 1,
+    StandartDriver = 2,
+};
+
+//TODO add trim config
+pub const SOSC_Config = struct {
+    freq_hz: usize = 8_000_000,
+    erefs: EREFS,
+    valid_int_en: bool = false,
+    monitor_en: bool = false,
+    stop_mode_en: bool = true,
+};
+
+//TODO: add trim confg
+pub const FROLF_Config = struct {
+    en_periph_gate: bool = true,
+};
+
+pub const FROHF_Config = struct {
+    fro_hf_div: u4 = 0,
+    en_slow_periph_gate: bool = true,
+    en_fast_periph_gate: bool = true,
+    stop_en: bool = true,
+    error_int_en: bool = false,
+    firc_ready_int_en: bool = false,
+    freq: FIRC_FREQ = .@"48Mhz",
+};
+pub const Power_Config = struct {
+    driver: Drive_Mode = .MidDriver,
+};
+
+pub const Clock_Config = struct {
+    socs: ?SOSC_Config = null,
+    frohf: ?FROHF_Config = FROHF_Config{},
+    frolf: ?FROLF_Config = FROLF_Config{},
+    power: Power_Config = .{},
+    clock_source: System_Clock = .FRIC,
+    ahb_div: u8 = 0,
+    slow_clock_en: bool = true,
+};
+
+pub const Clock_Frequencies = struct {
+    clk_16k_0: usize = 16_384,
+    clk_16k_1: usize = 16_384,
+    clk_in: usize = 0,
+    fro_hf: usize = 0,
+    fro_hf_div: usize = 0,
+    clk_48m: usize = 0,
+    fro_12m: usize = 0,
+    clk_1m: usize = 1_000_000,
+    main_clk: usize = 0,
+    cpu_clk: usize = 0,
+    system_clk: usize = 0,
+    slow_clk: usize = 0,
+
+    pub fn maxForMode(mode: Drive_Mode) Clock_Frequencies {
+        return switch (mode) {
+            .MidDriver => .{
+                .clk_16k_0 = 16_384,
+                .clk_16k_1 = 16_384,
+                .clk_in = 50_000_000,
+                .fro_hf = 96_000_000,
+                .fro_hf_div = 48_000_000,
+                .clk_48m = 48_000_000,
+                .fro_12m = 12_000_000,
+                .clk_1m = 1_000_000,
+                .main_clk = 96_000_000,
+                .cpu_clk = 48_000_000,
+                .system_clk = 48_000_000,
+                .slow_clk = 12_000_000,
+            },
+            .StandartDriver => .{
+                .clk_16k_0 = 16_384,
+                .clk_16k_1 = 16_384,
+                .clk_in = 50_000_000,
+                .fro_hf = 192_000_000,
+                .fro_hf_div = 96_000_000,
+                .clk_48m = 48_000_000,
+                .fro_12m = 12_000_000,
+                .clk_1m = 1_000_000,
+                .main_clk = 192_000_000,
+                .cpu_clk = 96_000_000,
+                .system_clk = 96_000_000,
+                .slow_clk = 24_000_000,
+            },
+        };
+    }
+
+    pub fn validate(self: Clock_Frequencies, mode: Drive_Mode) !void {
+        const max_values = maxForMode(mode);
+
+        inline for (@typeInfo(@This()).@"struct".field_names) |name| {
+            const current = @field(self, name);
+            const max_allowed = @field(max_values, name);
+
+            if (current > max_allowed) {
+                return error.Overflow;
+            }
+        }
+    }
+};
+
+pub fn clock_init(comptime config: Clock_Config) !void {
+    const inner_clocks = comptime calc_clock(config);
+    unlock_clock_configuration();
+    inner_init(inner_clocks, config);
+    freeze_clock_configuration();
+    clocks = inner_clocks;
+}
+
+fn calc_clock(comptime config: Clock_Config) Clock_Frequencies {
+    var out_clk = Clock_Frequencies{};
+    if (config.socs) |ext| {
+        out_clk.clk_in = ext.freq_hz;
+    }
+    if (config.frohf) |hf| {
+        out_clk.fro_hf = switch (hf.freq) {
+            .@"192Mhz" => 192_000_000,
+            .@"96Mhz" => 96_000_000,
+            .@"64Mhz" => 64_000_000,
+            .@"48Mhz" => 48_000_000,
+        };
+
+        if (hf.en_slow_periph_gate) {
+            out_clk.clk_48m = 48_000_000;
+        }
+        out_clk.fro_hf_div = out_clk.fro_hf / (hf.fro_hf_div + 1);
+    }
+
+    if (config.socs) |_| {
+        @compileError("SOCS IS NOT SUPPORTED YET");
+    }
+
+    switch (config.clock_source) {
+        .FRIC => {
+            if (out_clk.fro_hf == 0) @compileError("MAIN CLOCK USE FRO_HF BUT FRO_HF IS DISABLED IN THIS CONFIG");
+            out_clk.main_clk = out_clk.fro_hf;
+        },
+        .SIRC => {
+            if (out_clk.fro_12m == 0) @compileError("MAIN CLOCK USE FRO_LF BUT FRO_LF IS DISABLED IN THIS CONFIG");
+            out_clk.main_clk = out_clk.fro_12m;
+        },
+        else => {
+            @compileError("MODE: " ++ @tagName(config.clock_source) ++ " IS NOT SUPPORTED YET");
+        },
+    }
+
+    out_clk.cpu_clk = out_clk.main_clk / (config.ahb_div + 1);
+    out_clk.system_clk = out_clk.cpu_clk;
+    out_clk.slow_clk = out_clk.cpu_clk / 4;
+    out_clk.validate(config.power.driver) catch @compileError("INVALID CLOCK CONFIG");
+    return out_clk;
+}
+
+fn inner_init(comptime clks: Clock_Frequencies, config: Clock_Config) void {
+    //First put the hardware in a safe state:
+    safe_init();
+    power_and_flash(clks.cpu_clk, config.power);
+
+    //enable clocks
+    enable_clocks(config);
+
+    //set main clk
+    syscon.AHBCLKDIV.modify_one("DIV", config.ahb_div);
+    while (syscon.AHBCLKDIV.read().UNSTAB == .ONGOING) {}
+
+    scg0.RCCR.modify_one("SCS", @fromBackingInt(@intCast(@backingInt(config.clock_source))));
+    while (@backingInt(scg0.CSR.read().SCS) != @backingInt(config.clock_source)) {}
+}
+
+fn safe_init() void {
+    //set SIRC as the main clk, fro12_hf is always valid no matter the actual flash and power config
+    //also, FRO_HF cannot be configured while used as the main_clk
+    scg0.SIRCCSR.modify_one("LK", .WRITE_ENABLED);
+
+    scg0.SIRCCSR.modify_one("SIRC_CLK_PERIPH_EN", .ENABLED);
+
+    while (scg0.SIRCCSR.read().SIRCVLD == .DISABLED_OR_NOT_VALID) {}
+
+    if (scg0.SIRCCSR.read().SIRCERR == .ERROR_DETECTED) @panic("CLOCK INIT FAIL");
+
+    scg0.RCCR.modify_one("SCS", .SIRC);
+    while (scg0.CSR.read().SCS != .SIRC) {}
+    scg0.SIRCCSR.modify_one("LK", .WRITE_DISABLED);
+}
+
+//TODO ALLOW FOR LP_CONFG and add bandgap/DS checks
+fn power_and_flash(cpu_clk: usize, power_cfg: Power_Config) void {
+    //enable bandgap
+
+    //no config for DS and bandgap yet, so force normal mode
+    spc0.ACTIVE_CFG.modify_one("BGMODE", .BGMODE01);
+    spc0.ACTIVE_CFG.modify_one("CORELDO_VDD_DS", .NORMAL);
+
+    spc0.ACTIVE_CFG.modify_one("CORELDO_VDD_LVL", @fromBackingInt(@intCast(@backingInt(power_cfg.driver))));
+    while (spc0.SC.read().BUSY == .BUSY_YES) {}
+    FMU.FCTRL.modify_one("RWSC", get_flash_wait_states(power_cfg.driver, cpu_clk));
+
+    spc0.SRAMCTL.modify_one("VSM", @fromBackingInt(@intCast(@backingInt(power_cfg.driver))));
+    spc0.SRAMCTL.modify_one("REQ", .REQ_YES);
+    while (spc0.SRAMCTL.read().ACK == .ACK_NO) {}
+    spc0.SRAMCTL.modify_one("REQ", .REQ_NO);
+}
+
+fn enable_clocks(config: Clock_Config) void {
+    //SOCS and ROSC not supported yet, SIRC already enabled
+
+    scg0.FIRCCSR.modify_one("LK", .WRITE_ENABLED);
+    scg0.FIRCCSR.modify_one("FIRCTREN", .DISABLED);
+
+    if (config.frohf) |hf| {
+        scg0.FIRCCSR.write(.{
+            .FIRC_FCLK_PERIPH_EN = @fromBackingInt(@intCast(@intFromBool(hf.en_fast_periph_gate))),
+            .FIRC_SCLK_PERIPH_EN = @fromBackingInt(@intCast(@intFromBool(hf.en_slow_periph_gate))),
+            .FIRCACC_IE = @fromBackingInt(@intCast(@intFromBool(hf.firc_ready_int_en))),
+            .FIRCERR_IE = @fromBackingInt(@intCast(@intFromBool(hf.error_int_en))),
+            .FIRCSTEN = @fromBackingInt(@intCast(@intFromBool(hf.stop_en))),
+            .LK = .WRITE_ENABLED, //leep lk open
+            .FIRCACC = .NOT_ENABLED_OR_NOT_VALID, //not modify
+        });
+        scg0.FIRCCSR.modify_one("FIRCTREN", .ENABLED);
+        scg0.FIRCCFG.modify_one("FREQ_SEL", @fromBackingInt(@intCast(@backingInt(hf.freq))));
+
+        while (scg0.FIRCCSR.read().FIRCVLD == .NOT_ENABLED_OR_NOT_VALID) {}
+        if (scg0.FIRCCSR.read().FIRCERR == .ERROR_DETECTED) @panic("CLOCK INIT FAIL");
+
+        //apply fro_hf_div
+        MRCC0.MRCC_FRO_HF_DIV_CLKDIV.modify_one("DIV", hf.fro_hf_div);
+        while (MRCC0.MRCC_FRO_HF_DIV_CLKDIV.read().UNSTAB == .OFF) {}
+    }
+    scg0.FIRCCSR.modify_one("LK", .WRITE_DISABLED);
+}
+
+fn get_flash_wait_states(mode: Drive_Mode, cpu_clk: usize) u4 {
+    switch (mode) {
+        .MidDriver => return if (cpu_clk >= 24_000_000) 1 else 0,
+        .StandartDriver => {
+            if (cpu_clk <= 30_000_000) {
+                return 0;
+            } else if (cpu_clk <= 60_000_000) {
+                return 1;
+            } else if (cpu_clk <= 90_000_000) {
+                return 2;
+            } else return 3;
+        },
+    }
+}