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[SimToSV] Implement sim.proc.print lowering logic
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‎lib/Conversion/SimToSV/SimToSV.cpp‎

Lines changed: 225 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,8 @@
2525
#include "mlir/IR/Threading.h"
2626
#include "mlir/Pass/Pass.h"
2727
#include "mlir/Transforms/DialectConversion.h"
28+
#include "mlir/Transforms/RegionUtils.h"
29+
#include "llvm/ADT/SmallPtrSet.h"
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#define DEBUG_TYPE "lower-sim-to-sv"
3032

@@ -55,6 +57,162 @@ static std::pair<Value, Value> needsClockAndConditionWrapper(Operation *op) {
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5658
namespace {
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60+
static void appendLiteralToFWriteFormat(SmallString<128> &formatString,
61+
StringRef literal) {
62+
for (char ch : literal) {
63+
if (ch == '%')
64+
formatString += "%%";
65+
else
66+
formatString.push_back(ch);
67+
}
68+
}
69+
70+
static LogicalResult appendIntegerSpecifier(SmallString<128> &formatString,
71+
bool isLeftAligned,
72+
uint8_t paddingChar,
73+
std::optional<int32_t> width,
74+
char spec) {
75+
formatString.push_back('%');
76+
if (isLeftAligned)
77+
formatString.push_back('-');
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79+
// SystemVerilog formatting only has built-in support for '0' and ' '. Keep
80+
// this lowering strict to avoid silently changing formatting semantics.
81+
if (paddingChar == '0') {
82+
formatString.push_back('0');
83+
} else if (paddingChar != ' ') {
84+
return failure();
85+
}
86+
87+
if (width.has_value())
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formatString += std::to_string(width.value());
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formatString.push_back(spec);
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return success();
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}
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94+
static void appendFloatSpecifier(SmallString<128> &formatString,
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bool isLeftAligned,
96+
std::optional<int32_t> fieldWidth,
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int32_t fracDigits, char spec) {
98+
formatString.push_back('%');
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if (isLeftAligned)
100+
formatString.push_back('-');
101+
if (fieldWidth.has_value())
102+
formatString += std::to_string(fieldWidth.value());
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formatString.push_back('.');
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formatString += std::to_string(fracDigits);
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formatString.push_back(spec);
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}
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108+
static LogicalResult foldFormatStringToFWrite(
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Value input, SmallString<128> &formatString, SmallVectorImpl<Value> &args,
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llvm::SmallPtrSetImpl<Operation *> &visited, std::string &failureReason) {
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Operation *op = input.getDefiningOp();
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if (!op) {
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failureReason =
114+
"block argument format strings are unsupported as sim.proc.print input";
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return failure();
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}
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if (auto concat = dyn_cast<FormatStringConcatOp>(op)) {
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if (!visited.insert(op).second) {
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failureReason = "cyclic sim.fmt.concat is unsupported";
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return failure();
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}
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for (auto operand : concat.getInputs())
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if (failed(foldFormatStringToFWrite(operand, formatString, args, visited,
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failureReason)))
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return failure();
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visited.erase(op);
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return success();
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}
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return TypeSwitch<Operation *, LogicalResult>(op)
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.Case<FormatLiteralOp>([&](auto literal) -> LogicalResult {
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appendLiteralToFWriteFormat(formatString, literal.getLiteral());
134+
return success();
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})
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.Case<FormatHierPathOp>([&](auto hierPath) -> LogicalResult {
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formatString += hierPath.getUseEscapes() ? "%M" : "%m";
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return success();
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})
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.Case<FormatCharOp>([&](auto fmt) -> LogicalResult {
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formatString += "%c";
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatDecOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'd'))) {
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failureReason = "sim.fmt.dec only supports paddingChar 32 (' ') or "
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"48 ('0') for SystemVerilog lowering";
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return failure();
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatHexOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(
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formatString, fmt.getIsLeftAligned(), fmt.getPaddingChar(),
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fmt.getSpecifierWidth(),
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fmt.getIsHexUppercase() ? 'X' : 'x'))) {
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failureReason = "sim.fmt.hex only supports paddingChar 32 (' ') or "
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"48 ('0') for SystemVerilog lowering";
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return failure();
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatOctOp>([&](auto fmt) -> LogicalResult {
169+
if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'o'))) {
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failureReason = "sim.fmt.oct only supports paddingChar 32 (' ') or "
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"48 ('0') for SystemVerilog lowering";
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return failure();
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatBinOp>([&](auto fmt) -> LogicalResult {
180+
if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
181+
fmt.getPaddingChar(),
182+
fmt.getSpecifierWidth(), 'b'))) {
183+
failureReason = "sim.fmt.bin only supports paddingChar 32 (' ') or "
184+
"48 ('0') for SystemVerilog lowering";
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return failure();
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatScientificOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'e');
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatFloatOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'f');
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatGeneralOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'g');
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args.push_back(fmt.getValue());
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return success();
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})
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.Default([&](auto unsupportedOp) {
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failureReason = (Twine("unsupported format fragment '") +
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unsupportedOp->getName().getStringRef() + "'")
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.str();
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return failure();
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});
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}
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58216
struct SimConversionState {
59217
hw::HWModuleOp module;
60218
bool usedSynthesisMacro = false;
@@ -281,6 +439,62 @@ class DPICallLowering : public SimConversionPattern<DPICallOp> {
281439
}
282440
};
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namespace {
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class PrintFormattedProcLowering
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: public SimConversionPattern<PrintFormattedProcOp> {
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public:
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using SimConversionPattern<PrintFormattedProcOp>::SimConversionPattern;
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LogicalResult
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matchAndRewrite(PrintFormattedProcOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const final {
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SmallString<128> formatString;
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SmallVector<Value> args;
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std::string failureReason;
454+
llvm::SmallPtrSet<Operation *, 8> visited;
455+
if (failed(foldFormatStringToFWrite(op.getInput(), formatString, args,
456+
visited, failureReason))) {
457+
auto diag = op.emitError("cannot lower 'sim.proc.print' to sv.fwrite: ");
458+
diag << failureReason;
459+
return failure();
460+
}
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// Align with FIRRTLToHW: default to writing to stderr.
463+
// Specifying an output stream is not currently supported.
464+
auto fd =
465+
hw::ConstantOp::create(rewriter, op.getLoc(), APInt(32, 0x80000002));
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sv::FWriteOp::create(rewriter, op.getLoc(), fd, formatString, args);
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rewriter.eraseOp(op);
469+
return success();
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}
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};
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static LogicalResult validatePrintLowering(hw::HWModuleOp module) {
474+
LogicalResult result = success();
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module.walk([&](PrintFormattedOp op) {
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op.emitError("cannot lower 'sim.print' directly to SystemVerilog; run "
477+
"--sim-proceduralize first to convert it to "
478+
"'sim.proc.print'");
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result = failure();
480+
});
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module.walk([&](PrintFormattedProcOp op) {
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SmallString<128> formatString;
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SmallVector<Value> args;
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std::string failureReason;
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llvm::SmallPtrSet<Operation *, 8> visited;
487+
if (failed(foldFormatStringToFWrite(op.getInput(), formatString, args,
488+
visited, failureReason))) {
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auto diag = op.emitError("cannot lower 'sim.proc.print' to sv.fwrite: ");
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diag << failureReason;
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result = failure();
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}
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});
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return result;
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}
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}; // namespace
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// A helper struct to lower DPI function/call.
285499
struct LowerDPIFunc {
286500
llvm::DenseMap<StringAttr, StringAttr> symbolToFragment;
@@ -480,9 +694,16 @@ struct SimToSVPass : public circt::impl::LowerSimToSVBase<SimToSVPass> {
480694
if (moveOpsIntoIfdefGuardsAndProcesses(module))
481695
usedSynthesisMacro = true;
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697+
if (failed(validatePrintLowering(module)))
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return failure();
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483700
SimConversionState state;
484701
ConversionTarget target(*context);
485702
target.addIllegalDialect<SimDialect>();
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target.addLegalOp<FormatLiteralOp, FormatHierPathOp, FormatCharOp,
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FormatDecOp, FormatHexOp, FormatOctOp, FormatBinOp,
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FormatScientificOp, FormatFloatOp, FormatGeneralOp,
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FormatStringConcatOp>();
486707
target.addLegalDialect<sv::SVDialect>();
487708
target.addLegalDialect<hw::HWDialect>();
488709
target.addLegalDialect<seq::SeqDialect>();
@@ -496,11 +717,15 @@ struct SimToSVPass : public circt::impl::LowerSimToSVBase<SimToSVPass> {
496717
patterns.add<TerminateOp>(convert);
497718
patterns.add<PauseOp>(convert);
498719
patterns.add<DPICallLowering>(context, state);
720+
patterns.add<PrintFormattedProcLowering>(context, state);
499721
auto result = applyPartialConversion(module, target, std::move(patterns));
500722

501723
if (failed(result))
502724
return result;
503725

726+
mlir::IRRewriter rewriter(module);
727+
(void)mlir::runRegionDCE(rewriter, module->getRegions());
728+
504729
// Set the emit fragment.
505730
lowerDPIFunc.addFragments(module, state.dpiCallees.takeVector());
506731

‎test/Conversion/SimToSV/print-errors.mlir‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
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// RUN: circt-opt --lower-sim-to-sv --split-input-file --verify-diagnostics %s
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hw.module @unsupported_padding_char(in %arg : i8) {
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sv.initial {
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%lit = sim.fmt.literal "bad="
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%bad = sim.fmt.dec %arg paddingChar 42 specifierWidth 2 : i8
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%msg = sim.fmt.concat (%lit, %bad)
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// expected-error @below {{cannot lower 'sim.proc.print' to sv.fwrite: sim.fmt.dec only supports paddingChar 32 (' ') or 48 ('0') for SystemVerilog lowering}}
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sim.proc.print %msg
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}
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}
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// -----
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hw.module @unsupported_input_block_argument(in %arg : !sim.fstring) {
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sv.initial {
17+
// expected-error @below {{cannot lower 'sim.proc.print' to sv.fwrite: block argument format strings are unsupported as sim.proc.print input}}
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sim.proc.print %arg
19+
}
20+
}
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// -----
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hw.module @sim_print_requires_proceduralize(in %clk : !seq.clock, in %cond : i1) {
25+
%lit = sim.fmt.literal "hello"
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// expected-error @below {{cannot lower 'sim.print' directly to SystemVerilog; run --sim-proceduralize first to convert it to 'sim.proc.print'}}
27+
sim.print %lit on %clk if %cond
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}

‎test/Conversion/SimToSV/print.mlir‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
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// RUN: circt-opt --lower-sim-to-sv %s | FileCheck %s
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// CHECK-LABEL: hw.module @proc_print
4+
hw.module @proc_print(in %arg: i8) {
5+
// CHECK: sv.initial {
6+
sv.initial {
7+
%l0 = sim.fmt.literal "err: "
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%f0 = sim.fmt.hex %arg, isUpper true specifierWidth 2 : i8
9+
%l1 = sim.fmt.literal " 100%"
10+
%msg = sim.fmt.concat (%l0, %f0, %l1)
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// CHECK-NEXT: %[[FD:.+]] = hw.constant -2147483646 : i32
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// CHECK-NEXT: sv.fwrite %[[FD]], "err: %02X 100%%"(%arg) : i8
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// CHECK-NOT: sim.fmt.
15+
sim.proc.print %msg
16+
}
17+
}
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19+
// CHECK-LABEL: hw.module @all_format_fragments
20+
hw.module @all_format_fragments(in %ival : i16, in %ch : i8, in %fval : f64) {
21+
sv.initial {
22+
%i0 = sim.fmt.literal "dec="
23+
%f0 = sim.fmt.dec %ival specifierWidth 6 signed : i16
24+
%i1 = sim.fmt.literal " hex="
25+
%f1 = sim.fmt.hex %ival, isUpper true paddingChar 48 specifierWidth 4 : i16
26+
%i2 = sim.fmt.literal " oct="
27+
%f2 = sim.fmt.oct %ival isLeftAligned true specifierWidth 6 : i16
28+
%i3 = sim.fmt.literal " bin="
29+
%f3 = sim.fmt.bin %ival paddingChar 32 specifierWidth 8 : i16
30+
%i4 = sim.fmt.literal " char="
31+
%f4 = sim.fmt.char %ch : i8
32+
%i5 = sim.fmt.literal " exp="
33+
%f5 = sim.fmt.exp %fval fieldWidth 10 fracDigits 3 : f64
34+
%i6 = sim.fmt.literal " flt="
35+
%f6 = sim.fmt.flt %fval isLeftAligned true fieldWidth 8 fracDigits 2 : f64
36+
%i7 = sim.fmt.literal " gen="
37+
%f7 = sim.fmt.gen %fval fracDigits 4 : f64
38+
%i8 = sim.fmt.literal " path="
39+
%f8 = sim.fmt.hier_path
40+
%i9 = sim.fmt.literal " esc="
41+
%f9 = sim.fmt.hier_path escaped
42+
%i10 = sim.fmt.literal " pct=%"
43+
%msg = sim.fmt.concat (%i0, %f0, %i1, %f1, %i2, %f2, %i3, %f3, %i4, %f4, %i5, %f5, %i6, %f6, %i7, %f7, %i8, %f8, %i9, %f9, %i10)
44+
45+
// CHECK: %[[FD:.+]] = hw.constant -2147483646 : i32
46+
// CHECK-NEXT: sv.fwrite %[[FD]], "dec=%6d hex=%04X oct=%-06o bin=%8b char=%c exp=%10.3e flt=%-8.2f gen=%.4g path=%m esc=%M pct=%%"(%ival, %ival, %ival, %ival, %ch, %fval, %fval, %fval) : i16, i16, i16, i16, i8, f64, f64, f64
47+
// CHECK-NOT: sim.fmt.
48+
sim.proc.print %msg
49+
}
50+
}
51+
52+
// CHECK-LABEL: hw.module @nested_concat_order
53+
hw.module @nested_concat_order(in %lhs : i8, in %rhs : i8) {
54+
sv.initial {
55+
%l0 = sim.fmt.literal "L="
56+
%l1 = sim.fmt.literal ", R="
57+
%d0 = sim.fmt.dec %lhs specifierWidth 3 : i8
58+
%h0 = sim.fmt.hex %rhs, isUpper false specifierWidth 2 : i8
59+
60+
%c0 = sim.fmt.concat (%l0, %d0)
61+
%c1 = sim.fmt.concat (%c0, %l1)
62+
%c2 = sim.fmt.concat (%c1, %h0)
63+
64+
// CHECK: %[[FD:.+]] = hw.constant -2147483646 : i32
65+
// CHECK-NEXT: sv.fwrite %[[FD]], "L=%3d, R=%02x"(%lhs, %rhs) : i8, i8
66+
// CHECK-NOT: sim.fmt.
67+
sim.proc.print %c2
68+
}
69+
}

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