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[SimToSV] Implement sim.proc.print lowering logic
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‎lib/Conversion/SimToSV/SimToSV.cpp‎

Lines changed: 174 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,8 @@
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#include "mlir/IR/Threading.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "mlir/Transforms/RegionUtils.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#define DEBUG_TYPE "lower-sim-to-sv"
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@@ -55,6 +57,140 @@ static std::pair<Value, Value> needsClockAndConditionWrapper(Operation *op) {
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namespace {
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static void appendLiteralToFWriteFormat(SmallString<128> &formatString,
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StringRef literal) {
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for (char ch : literal) {
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if (ch == '%')
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formatString += "%%";
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else
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formatString.push_back(ch);
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}
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}
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static LogicalResult appendIntegerSpecifier(SmallString<128> &formatString,
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bool isLeftAligned,
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uint8_t paddingChar,
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std::optional<int32_t> width,
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char spec) {
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formatString.push_back('%');
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if (isLeftAligned)
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formatString.push_back('-');
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// SystemVerilog formatting only has built-in support for '0' and ' '. Keep
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// this lowering strict to avoid silently changing formatting semantics.
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if (paddingChar == '0') {
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formatString.push_back('0');
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} else if (paddingChar != ' ') {
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return failure();
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}
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if (width.has_value())
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formatString += std::to_string(width.value());
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formatString.push_back(spec);
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return success();
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}
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static void appendFloatSpecifier(SmallString<128> &formatString,
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bool isLeftAligned,
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std::optional<int32_t> fieldWidth,
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int32_t fracDigits, char spec) {
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formatString.push_back('%');
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if (isLeftAligned)
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formatString.push_back('-');
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if (fieldWidth.has_value())
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formatString += std::to_string(fieldWidth.value());
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formatString.push_back('.');
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formatString += std::to_string(fracDigits);
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formatString.push_back(spec);
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}
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static LogicalResult
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foldFormatStringToFWrite(Value input, SmallString<128> &formatString,
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SmallVectorImpl<Value> &args,
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llvm::SmallPtrSetImpl<Operation *> &visited) {
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Operation *op = input.getDefiningOp();
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if (!op)
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return failure();
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if (auto concat = dyn_cast<FormatStringConcatOp>(op)) {
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if (!visited.insert(op).second)
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return failure();
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for (auto operand : concat.getInputs())
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if (failed(
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foldFormatStringToFWrite(operand, formatString, args, visited)))
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return failure();
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visited.erase(op);
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return success();
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}
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return TypeSwitch<Operation *, LogicalResult>(op)
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.Case<FormatLiteralOp>([&](auto literal) -> LogicalResult {
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appendLiteralToFWriteFormat(formatString, literal.getLiteral());
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return success();
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})
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.Case<FormatHierPathOp>([&](auto hierPath) -> LogicalResult {
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formatString += hierPath.getUseEscapes() ? "%M" : "%m";
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return success();
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})
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.Case<FormatCharOp>([&](auto fmt) -> LogicalResult {
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formatString += "%c";
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatDecOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'd')))
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return failure();
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatHexOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(
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formatString, fmt.getIsLeftAligned(), fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), fmt.getIsHexUppercase() ? 'X' : 'x')))
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return failure();
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatOctOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'o')))
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return failure();
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatBinOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'b')))
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return failure();
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatScientificOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'e');
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatFloatOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'f');
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatGeneralOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'g');
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args.push_back(fmt.getValue());
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return success();
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})
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.Default([](auto) { return failure(); });
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}
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58194
struct SimConversionState {
59195
hw::HWModuleOp module;
60196
bool usedSynthesisMacro = false;
@@ -281,6 +417,36 @@ class DPICallLowering : public SimConversionPattern<DPICallOp> {
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}
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};
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namespace {
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class PrintFormattedProcLowering
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: public SimConversionPattern<PrintFormattedProcOp> {
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public:
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using SimConversionPattern<PrintFormattedProcOp>::SimConversionPattern;
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LogicalResult
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matchAndRewrite(PrintFormattedProcOp op, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const final {
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SmallString<128> formatString;
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SmallVector<Value> args;
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llvm::SmallPtrSet<Operation *, 8> visited;
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if (failed(foldFormatStringToFWrite(op.getInput(), formatString, args,
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visited)))
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return rewriter.notifyMatchFailure(
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op, "unsupported format fragment or integer padding char; only "
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"space and '0' padding are supported");
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// Align with FIRRTLToHW: default to writing to stderr.
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// Specifying an output stream is not currently supported.
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auto fd =
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hw::ConstantOp::create(rewriter, op.getLoc(), APInt(32, 0x80000002));
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sv::FWriteOp::create(rewriter, op.getLoc(), fd, formatString, args);
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rewriter.eraseOp(op);
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return success();
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}
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};
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}; // namespace
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// A helper struct to lower DPI function/call.
285451
struct LowerDPIFunc {
286452
llvm::DenseMap<StringAttr, StringAttr> symbolToFragment;
@@ -483,6 +649,10 @@ struct SimToSVPass : public circt::impl::LowerSimToSVBase<SimToSVPass> {
483649
SimConversionState state;
484650
ConversionTarget target(*context);
485651
target.addIllegalDialect<SimDialect>();
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target.addLegalOp<FormatLiteralOp, FormatHierPathOp, FormatCharOp,
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FormatDecOp, FormatHexOp, FormatOctOp, FormatBinOp,
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FormatScientificOp, FormatFloatOp, FormatGeneralOp,
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FormatStringConcatOp>();
486656
target.addLegalDialect<sv::SVDialect>();
487657
target.addLegalDialect<hw::HWDialect>();
488658
target.addLegalDialect<seq::SeqDialect>();
@@ -496,11 +666,15 @@ struct SimToSVPass : public circt::impl::LowerSimToSVBase<SimToSVPass> {
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patterns.add<TerminateOp>(convert);
497667
patterns.add<PauseOp>(convert);
498668
patterns.add<DPICallLowering>(context, state);
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patterns.add<PrintFormattedProcLowering>(context, state);
499670
auto result = applyPartialConversion(module, target, std::move(patterns));
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501672
if (failed(result))
502673
return result;
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mlir::IRRewriter rewriter(module);
676+
(void)mlir::runRegionDCE(rewriter, module->getRegions());
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504678
// Set the emit fragment.
505679
lowerDPIFunc.addFragments(module, state.dpiCallees.takeVector());
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‎test/Conversion/SimToSV/print-errors.mlir‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
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// RUN: circt-opt --lower-sim-to-sv --split-input-file --verify-diagnostics %s
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hw.module @unsupported_padding_char(in %arg : i8) {
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sv.initial {
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%lit = sim.fmt.literal "bad="
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%bad = sim.fmt.dec %arg paddingChar 42 specifierWidth 2 : i8
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%msg = sim.fmt.concat (%lit, %bad)
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// expected-error @below {{failed to legalize operation 'sim.proc.print'}}
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sim.proc.print %msg
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}
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}
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// -----
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hw.module @unsupported_input_block_argument(in %arg : !sim.fstring) {
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sv.initial {
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// expected-error @below {{failed to legalize operation 'sim.proc.print'}}
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sim.proc.print %arg
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}
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}

‎test/Conversion/SimToSV/print.mlir‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
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// RUN: circt-opt --lower-sim-to-sv %s | FileCheck %s
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// CHECK-LABEL: hw.module @proc_print
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hw.module @proc_print(in %arg: i8) {
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// CHECK: sv.initial {
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sv.initial {
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%l0 = sim.fmt.literal "err: "
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%f0 = sim.fmt.hex %arg, isUpper true specifierWidth 2 : i8
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%l1 = sim.fmt.literal " 100%"
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%msg = sim.fmt.concat (%l0, %f0, %l1)
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// CHECK-NEXT: %[[FD:.+]] = hw.constant -2147483646 : i32
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// CHECK-NEXT: sv.fwrite %[[FD]], "err: %02X 100%%"(%arg) : i8
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// CHECK-NOT: sim.fmt.
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sim.proc.print %msg
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}
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}
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// CHECK-LABEL: hw.module @all_format_fragments
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hw.module @all_format_fragments(in %ival : i16, in %ch : i8, in %fval : f64) {
21+
sv.initial {
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%i0 = sim.fmt.literal "dec="
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%f0 = sim.fmt.dec %ival specifierWidth 6 signed : i16
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%i1 = sim.fmt.literal " hex="
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%f1 = sim.fmt.hex %ival, isUpper true paddingChar 48 specifierWidth 4 : i16
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%i2 = sim.fmt.literal " oct="
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%f2 = sim.fmt.oct %ival isLeftAligned true specifierWidth 6 : i16
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%i3 = sim.fmt.literal " bin="
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%f3 = sim.fmt.bin %ival paddingChar 32 specifierWidth 8 : i16
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%i4 = sim.fmt.literal " char="
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%f4 = sim.fmt.char %ch : i8
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%i5 = sim.fmt.literal " exp="
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%f5 = sim.fmt.exp %fval fieldWidth 10 fracDigits 3 : f64
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%i6 = sim.fmt.literal " flt="
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%f6 = sim.fmt.flt %fval isLeftAligned true fieldWidth 8 fracDigits 2 : f64
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%i7 = sim.fmt.literal " gen="
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%f7 = sim.fmt.gen %fval fracDigits 4 : f64
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%i8 = sim.fmt.literal " path="
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%f8 = sim.fmt.hier_path
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%i9 = sim.fmt.literal " esc="
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%f9 = sim.fmt.hier_path escaped
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%i10 = sim.fmt.literal " pct=%"
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%msg = sim.fmt.concat (%i0, %f0, %i1, %f1, %i2, %f2, %i3, %f3, %i4, %f4, %i5, %f5, %i6, %f6, %i7, %f7, %i8, %f8, %i9, %f9, %i10)
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// CHECK: %[[FD:.+]] = hw.constant -2147483646 : i32
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// CHECK-NEXT: sv.fwrite %[[FD]], "dec=%6d hex=%04X oct=%-06o bin=%8b char=%c exp=%10.3e flt=%-8.2f gen=%.4g path=%m esc=%M pct=%%"(%ival, %ival, %ival, %ival, %ch, %fval, %fval, %fval) : i16, i16, i16, i16, i8, f64, f64, f64
47+
// CHECK-NOT: sim.fmt.
48+
sim.proc.print %msg
49+
}
50+
}
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// CHECK-LABEL: hw.module @nested_concat_order
53+
hw.module @nested_concat_order(in %lhs : i8, in %rhs : i8) {
54+
sv.initial {
55+
%l0 = sim.fmt.literal "L="
56+
%l1 = sim.fmt.literal ", R="
57+
%d0 = sim.fmt.dec %lhs specifierWidth 3 : i8
58+
%h0 = sim.fmt.hex %rhs, isUpper false specifierWidth 2 : i8
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60+
%c0 = sim.fmt.concat (%l0, %d0)
61+
%c1 = sim.fmt.concat (%c0, %l1)
62+
%c2 = sim.fmt.concat (%c1, %h0)
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64+
// CHECK: %[[FD:.+]] = hw.constant -2147483646 : i32
65+
// CHECK-NEXT: sv.fwrite %[[FD]], "L=%3d, R=%02x"(%lhs, %rhs) : i8, i8
66+
// CHECK-NOT: sim.fmt.
67+
sim.proc.print %c2
68+
}
69+
}

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