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[Sim] Implement the lowering logic from sim.proc.print to the SV dialect.
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‎include/circt/Dialect/Sim/SimPasses.td‎

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@@ -32,4 +32,10 @@ def LowerDPIFunc : Pass<"sim-lower-dpi-func", "mlir::ModuleOp"> {
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let dependentDialects = ["mlir::func::FuncDialect", "mlir::LLVM::LLVMDialect"];
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}
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def LowerPrintFormattedProcToSV
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: Pass<"sim-lower-print-formatted-proc-to-sv", "hw::HWModuleOp"> {
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let summary = "Lower sim.proc.print formatting ops to sv.fwrite";
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let dependentDialects = ["circt::hw::HWDialect", "circt::sv::SVDialect"];
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}
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#endif // CIRCT_DIALECT_SIM_SEQPASSES

‎lib/Dialect/Sim/Transforms/CMakeLists.txt‎

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@@ -1,6 +1,7 @@
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add_circt_dialect_library(CIRCTSimTransforms
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FoldValueFormatters.cpp
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LowerDPIFunc.cpp
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LowerPrintFormattedProcToSV.cpp
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ProceduralizeSim.cpp
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‎lib/Dialect/Sim/Transforms/LowerPrintFormattedProcToSV.cpp‎

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//===- LowerPrintFormattedProcToSV.cpp - Lower proc.print to sv.fwrite ---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass lowers sim.proc.print to sv.fwrite.
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//
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//===----------------------------------------------------------------------===//
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#include "circt/Dialect/HW/HWOps.h"
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#include "circt/Dialect/SV/SVOps.h"
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#include "circt/Dialect/Sim/SimOps.h"
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#include "circt/Dialect/Sim/SimPasses.h"
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#include "mlir/IR/Builders.h"
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#include "mlir/IR/PatternMatch.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/RegionUtils.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#define DEBUG_TYPE "sim-lower-print-formatted-proc-to-sv"
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namespace circt {
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namespace sim {
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#define GEN_PASS_DEF_LOWERPRINTFORMATTEDPROCTOSV
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#include "circt/Dialect/Sim/SimPasses.h.inc"
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} // namespace sim
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} // namespace circt
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using namespace circt;
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using namespace sim;
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namespace {
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static void appendLiteralToFWriteFormat(SmallString<128> &formatString,
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StringRef literal) {
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for (char ch : literal) {
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if (ch == '%')
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formatString += "%%";
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else
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formatString.push_back(ch);
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}
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}
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static LogicalResult appendIntegerSpecifier(SmallString<128> &formatString,
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bool isLeftAligned,
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uint8_t paddingChar,
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std::optional<int32_t> width,
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char spec) {
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formatString.push_back('%');
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if (isLeftAligned)
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formatString.push_back('-');
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// SystemVerilog formatting only has built-in support for '0' and ' '. Keep
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// this lowering strict to avoid silently changing formatting semantics.
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if (paddingChar == '0') {
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formatString.push_back('0');
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} else if (paddingChar != ' ') {
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return failure();
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}
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if (width.has_value())
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formatString += std::to_string(width.value());
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formatString.push_back(spec);
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return success();
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}
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static void appendFloatSpecifier(SmallString<128> &formatString,
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bool isLeftAligned,
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std::optional<int32_t> fieldWidth,
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int32_t fracDigits, char spec) {
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formatString.push_back('%');
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if (isLeftAligned)
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formatString.push_back('-');
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if (fieldWidth.has_value())
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formatString += std::to_string(fieldWidth.value());
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formatString.push_back('.');
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formatString += std::to_string(fracDigits);
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formatString.push_back(spec);
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}
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static LogicalResult
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getFlattenedFormatFragments(Value input, SmallVectorImpl<Value> &fragments,
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std::string &failureReason) {
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if (auto concat = input.getDefiningOp<FormatStringConcatOp>()) {
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if (failed(concat.getFlattenedInputs(fragments))) {
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failureReason = "cyclic sim.fmt.concat is unsupported";
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return failure();
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}
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return success();
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}
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fragments.push_back(input);
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return success();
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}
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static LogicalResult
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appendFormatFragmentToFWrite(Value fragment, SmallString<128> &formatString,
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SmallVectorImpl<Value> &args,
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std::string &failureReason) {
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Operation *fragmentOp = fragment.getDefiningOp();
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if (!fragmentOp) {
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failureReason =
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"block argument format strings are unsupported as sim.proc.print input";
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return failure();
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}
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return TypeSwitch<Operation *, LogicalResult>(fragmentOp)
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.Case<FormatLiteralOp>([&](auto literal) -> LogicalResult {
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appendLiteralToFWriteFormat(formatString, literal.getLiteral());
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return success();
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})
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.Case<FormatHierPathOp>([&](auto hierPath) -> LogicalResult {
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formatString += hierPath.getUseEscapes() ? "%M" : "%m";
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return success();
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})
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.Case<FormatCharOp>([&](auto fmt) -> LogicalResult {
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formatString += "%c";
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatDecOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'd'))) {
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failureReason = "sim.fmt.dec only supports paddingChar 32 (' ') or "
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"48 ('0') for SystemVerilog lowering";
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return failure();
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatHexOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(
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formatString, fmt.getIsLeftAligned(), fmt.getPaddingChar(),
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fmt.getSpecifierWidth(),
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fmt.getIsHexUppercase() ? 'X' : 'x'))) {
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failureReason = "sim.fmt.hex only supports paddingChar 32 (' ') or "
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"48 ('0') for SystemVerilog lowering";
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return failure();
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatOctOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'o'))) {
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failureReason = "sim.fmt.oct only supports paddingChar 32 (' ') or "
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"48 ('0') for SystemVerilog lowering";
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return failure();
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatBinOp>([&](auto fmt) -> LogicalResult {
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if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getPaddingChar(),
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fmt.getSpecifierWidth(), 'b'))) {
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failureReason = "sim.fmt.bin only supports paddingChar 32 (' ') or "
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"48 ('0') for SystemVerilog lowering";
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return failure();
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}
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatScientificOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'e');
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatFloatOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'f');
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args.push_back(fmt.getValue());
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return success();
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})
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.Case<FormatGeneralOp>([&](auto fmt) -> LogicalResult {
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appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
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fmt.getFieldWidth(), fmt.getFracDigits(), 'g');
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args.push_back(fmt.getValue());
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return success();
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})
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.Default([&](auto unsupportedOp) {
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failureReason = (Twine("unsupported format fragment '") +
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unsupportedOp->getName().getStringRef() + "'")
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.str();
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return failure();
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});
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}
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static LogicalResult foldFormatStringToFWrite(Value input,
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SmallString<128> &formatString,
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SmallVectorImpl<Value> &args,
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std::string &failureReason) {
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SmallVector<Value, 8> fragments;
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if (failed(getFlattenedFormatFragments(input, fragments, failureReason)))
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return failure();
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for (auto fragment : fragments)
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if (failed(appendFormatFragmentToFWrite(fragment, formatString, args,
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failureReason)))
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return failure();
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return success();
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}
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struct LowerPrintFormattedProcToSVPass
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: public impl::LowerPrintFormattedProcToSVBase<
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LowerPrintFormattedProcToSVPass> {
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void runOnOperation() override {
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auto module = getOperation();
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bool sawError = false;
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SmallVector<PrintFormattedProcOp> printOps;
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module.walk([&](PrintFormattedProcOp op) { printOps.push_back(op); });
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llvm::SmallPtrSet<Operation *, 8> dceRoots;
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for (auto printOp : printOps) {
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SmallString<128> formatString;
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SmallVector<Value> args;
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std::string failureReason;
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if (failed(foldFormatStringToFWrite(printOp.getInput(), formatString,
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args, failureReason))) {
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auto diag =
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printOp.emitError("cannot lower 'sim.proc.print' to sv.fwrite: ");
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diag << failureReason;
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sawError = true;
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continue;
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}
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OpBuilder builder(printOp);
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// Align with FIRRTLToHW: default to writing to stderr.
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// Specifying an output stream is not currently supported.
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auto fd = hw::ConstantOp::create(builder, printOp.getLoc(),
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APInt(32, 0x80000002));
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sv::FWriteOp::create(builder, printOp.getLoc(), fd, formatString, args);
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if (Operation *parent = printOp->getParentOp())
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dceRoots.insert(parent);
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printOp.erase();
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}
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if (sawError)
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return signalPassFailure();
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mlir::IRRewriter rewriter(module);
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for (Operation *dceRoot : dceRoots)
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(void)mlir::runRegionDCE(rewriter, dceRoot->getRegions());
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}
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};
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} // namespace

‎test/Dialect/Sim/lower-print-formatted-proc-to-sv-errors.mlir‎

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// RUN: circt-opt --sim-lower-print-formatted-proc-to-sv --split-input-file --verify-diagnostics %s
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hw.module @unsupported_padding_char(in %arg : i8) {
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sv.initial {
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%lit = sim.fmt.literal "bad="
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%bad = sim.fmt.dec %arg paddingChar 42 specifierWidth 2 : i8
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%msg = sim.fmt.concat (%lit, %bad)
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// expected-error @below {{cannot lower 'sim.proc.print' to sv.fwrite: sim.fmt.dec only supports paddingChar 32 (' ') or 48 ('0') for SystemVerilog lowering}}
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sim.proc.print %msg
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}
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}
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// -----
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hw.module @unsupported_input_block_argument(in %arg : !sim.fstring) {
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sv.initial {
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// expected-error @below {{cannot lower 'sim.proc.print' to sv.fwrite: block argument format strings are unsupported as sim.proc.print input}}
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sim.proc.print %arg
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}
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}

‎test/Dialect/Sim/lower-print-formatted-proc-to-sv.mlir‎

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// RUN: circt-opt --sim-lower-print-formatted-proc-to-sv %s | FileCheck %s
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// CHECK-LABEL: hw.module @proc_print
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hw.module @proc_print(in %arg: i8) {
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// CHECK: sv.initial {
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sv.initial {
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%l0 = sim.fmt.literal "err: "
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%f0 = sim.fmt.hex %arg, isUpper true specifierWidth 2 : i8
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%l1 = sim.fmt.literal " 100%"
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%msg = sim.fmt.concat (%l0, %f0, %l1)
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// CHECK-NEXT: %[[FD:.+]] = hw.constant -2147483646 : i32
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// CHECK-NEXT: sv.fwrite %[[FD]], "err: %02X 100%%"(%arg) : i8
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// CHECK-NOT: sim.fmt.
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sim.proc.print %msg
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}
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}
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// CHECK-LABEL: hw.module @all_format_fragments
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hw.module @all_format_fragments(in %ival : i16, in %ch : i8, in %fval : f64) {
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sv.initial {
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%i0 = sim.fmt.literal "dec="
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%f0 = sim.fmt.dec %ival specifierWidth 6 signed : i16
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%i1 = sim.fmt.literal " hex="
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%f1 = sim.fmt.hex %ival, isUpper true paddingChar 48 specifierWidth 4 : i16
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%i2 = sim.fmt.literal " oct="
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%f2 = sim.fmt.oct %ival isLeftAligned true specifierWidth 6 : i16
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%i3 = sim.fmt.literal " bin="
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%f3 = sim.fmt.bin %ival paddingChar 32 specifierWidth 8 : i16
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%i4 = sim.fmt.literal " char="
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%f4 = sim.fmt.char %ch : i8
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%i5 = sim.fmt.literal " exp="
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%f5 = sim.fmt.exp %fval fieldWidth 10 fracDigits 3 : f64
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%i6 = sim.fmt.literal " flt="
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%f6 = sim.fmt.flt %fval isLeftAligned true fieldWidth 8 fracDigits 2 : f64
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%i7 = sim.fmt.literal " gen="
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%f7 = sim.fmt.gen %fval fracDigits 4 : f64
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%i8 = sim.fmt.literal " path="
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%f8 = sim.fmt.hier_path
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%i9 = sim.fmt.literal " esc="
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%f9 = sim.fmt.hier_path escaped
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%i10 = sim.fmt.literal " pct=%"
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%msg = sim.fmt.concat (%i0, %f0, %i1, %f1, %i2, %f2, %i3, %f3, %i4, %f4, %i5, %f5, %i6, %f6, %i7, %f7, %i8, %f8, %i9, %f9, %i10)
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// CHECK: %[[FD:.+]] = hw.constant -2147483646 : i32
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// CHECK-NEXT: sv.fwrite %[[FD]], "dec=%6d hex=%04X oct=%-06o bin=%8b char=%c exp=%10.3e flt=%-8.2f gen=%.4g path=%m esc=%M pct=%%"(%ival, %ival, %ival, %ival, %ch, %fval, %fval, %fval) : i16, i16, i16, i16, i8, f64, f64, f64
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// CHECK-NOT: sim.fmt.
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sim.proc.print %msg
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}
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}
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// CHECK-LABEL: hw.module @nested_concat_order
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hw.module @nested_concat_order(in %lhs : i8, in %rhs : i8) {
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sv.initial {
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%l0 = sim.fmt.literal "L="
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%l1 = sim.fmt.literal ", R="
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%d0 = sim.fmt.dec %lhs specifierWidth 3 : i8
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%h0 = sim.fmt.hex %rhs, isUpper false specifierWidth 2 : i8
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%c0 = sim.fmt.concat (%l0, %d0)
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%c1 = sim.fmt.concat (%c0, %l1)
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%c2 = sim.fmt.concat (%c1, %h0)
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// CHECK: %[[FD:.+]] = hw.constant -2147483646 : i32
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// CHECK-NEXT: sv.fwrite %[[FD]], "L=%3d, R=%02x"(%lhs, %rhs) : i8, i8
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// CHECK-NOT: sim.fmt.
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sim.proc.print %c2
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}
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}

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