FPGA: pull the fft2d sample out of 2024.2 (#2355)

This sample exposes an issue that results in incorrect results out of an FPGA run using 2024.2.
It is unclear at this time if the issue in coming from the compiler, the runtime, the BSP or the hardware.
The sample is being pulled out until the root cause has been understood.

Author: intel-jisheng1

DirectProgramming/C++SYCL_FPGA/README.md

@@ -181,7 +181,6 @@ All the Tier 4 samples are in the [ReferenceDesigns](ReferenceDesigns) category.
 | [crr](ReferenceDesigns/crr)                               | How to implement the Cox-Ross-Rubinstein (CRR) binomial tree model on a FPGA
 | [db](ReferenceDesigns/db)                                 | How to accelerate database queries using an FPGA
 | [decompress](ReferenceDesigns/decompress)                 | How to implement an efficient GZIP and Snappy decompression engine on a FPGA
-| [fft2d](ReferenceDesigns/fft2d)                           | How to implement an efficient 2D FFT on a FPGA
 | [gzip](ReferenceDesigns/gzip)                             | How to implement a high-performance multi-engine compression algorithm on FPGA
 | [matmul](ReferenceDesigns/matmul)                         | How to implement a systolic-array-based high-performance matrix multiplication algorithm on FPGA
 | [merge_sort](ReferenceDesigns/merge_sort)                 | How to use the spatial compute of the FPGA to create a merge sort design that takes advantage of thread- and SIMD-level parallelism