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finley1226rkhuangtao
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clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type
The div offset of some clocks are different from their mux offset and the COMPOSITE clock-type require that div and mux offset are the same, so add a new COMPOSITE_DIV_OFFSET clock-type to handle that. Change-Id: I7d541e29328f37d2ad806b3b6e5ab35b5513b345 Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
1 parent ba98e18 commit 421e14f

2 files changed

Lines changed: 29 additions & 3 deletions

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drivers/clk/rockchip/clk.c

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@
4545
static struct clk *rockchip_clk_register_branch(const char *name,
4646
const char *const *parent_names, u8 num_parents, void __iomem *base,
4747
int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
48-
u8 div_shift, u8 div_width, u8 div_flags,
48+
int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
4949
struct clk_div_table *div_table, int gate_offset,
5050
u8 gate_shift, u8 gate_flags, unsigned long flags,
5151
spinlock_t *lock)
@@ -89,7 +89,10 @@ static struct clk *rockchip_clk_register_branch(const char *name,
8989
goto err_div;
9090

9191
div->flags = div_flags;
92-
div->reg = base + muxdiv_offset;
92+
if (div_offset)
93+
div->reg = base + div_offset;
94+
else
95+
div->reg = base + muxdiv_offset;
9396
div->shift = div_shift;
9497
div->width = div_width;
9598
div->lock = lock;
@@ -538,7 +541,7 @@ void __init rockchip_clk_register_branches(
538541
list->parent_names, list->num_parents,
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ctx->reg_base, list->muxdiv_offset, list->mux_shift,
540543
list->mux_width, list->mux_flags,
541-
list->div_shift, list->div_width,
544+
list->div_offset, list->div_shift, list->div_width,
542545
list->div_flags, list->div_table,
543546
list->gate_offset, list->gate_shift,
544547
list->gate_flags, flags, &ctx->lock);

drivers/clk/rockchip/clk.h

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -440,6 +440,7 @@ struct rockchip_clk_branch {
440440
u8 mux_shift;
441441
u8 mux_width;
442442
u8 mux_flags;
443+
int div_offset;
443444
u8 div_shift;
444445
u8 div_width;
445446
u8 div_flags;
@@ -472,6 +473,28 @@ struct rockchip_clk_branch {
472473
.gate_flags = gf, \
473474
}
474475

476+
#define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \
477+
mf, do, ds, dw, df, go, gs, gf) \
478+
{ \
479+
.id = _id, \
480+
.branch_type = branch_composite, \
481+
.name = cname, \
482+
.parent_names = pnames, \
483+
.num_parents = ARRAY_SIZE(pnames), \
484+
.flags = f, \
485+
.muxdiv_offset = mo, \
486+
.mux_shift = ms, \
487+
.mux_width = mw, \
488+
.mux_flags = mf, \
489+
.div_offset = do, \
490+
.div_shift = ds, \
491+
.div_width = dw, \
492+
.div_flags = df, \
493+
.gate_offset = go, \
494+
.gate_shift = gs, \
495+
.gate_flags = gf, \
496+
}
497+
475498
#define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
476499
go, gs, gf) \
477500
{ \

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