diff --git a/crates/core_arch/src/riscv32/mod.rs b/crates/core_arch/src/riscv32/mod.rs index 7ff871227b..7017b7edc4 100644 --- a/crates/core_arch/src/riscv32/mod.rs +++ b/crates/core_arch/src/riscv32/mod.rs @@ -1,6 +1,10 @@ //! RISC-V RV32 specific intrinsics +mod zb; mod zk; +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +pub use zb::*; + #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub use zk::*; diff --git a/crates/core_arch/src/riscv32/zb.rs b/crates/core_arch/src/riscv32/zb.rs new file mode 100644 index 0000000000..1639890baf --- /dev/null +++ b/crates/core_arch/src/riscv32/zb.rs @@ -0,0 +1,137 @@ +#[cfg(test)] +use stdarch_test::assert_instr; + +unsafe extern "llvm-intrinsic" { + #[link_name = "llvm.riscv.xperm8.i32"] + fn _xperm8_32(rs1: u32, rs2: u32) -> u32; + + #[link_name = "llvm.riscv.xperm4.i32"] + fn _xperm4_32(rs1: u32, rs2: u32) -> u32; + + #[link_name = "llvm.riscv.clmulh.i32"] + fn _clmulh_32(rs1: u32, rs2: u32) -> u32; + + #[link_name = "llvm.riscv.clmulr.i32"] + fn _clmulr_32(rs1: u32, rs2: u32) -> u32; + + #[link_name = "llvm.riscv.zip.i32"] + fn _zip_32(rs1: u32) -> u32; + + #[link_name = "llvm.riscv.unzip.i32"] + fn _unzip_32(rs1: u32) -> u32; +} + +/// Byte-wise lookup of indices into a vector in registers. +/// +/// The xperm8 instruction operates on bytes. The rs1 register contains a vector of 4 +/// 8-bit elements. The rs2 register contains a vector of 4 8-bit indexes. The result is +/// each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 +/// is out of bounds. +/// +/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions +/// +/// Version: v1.0.1 +/// +/// Section: 3.47 +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +#[target_feature(enable = "zbkx")] +#[cfg_attr(test, assert_instr(xperm8))] +#[inline] +pub fn xperm8_32(rs1: u32, rs2: u32) -> u32 { + unsafe { _xperm8_32(rs1, rs2) } +} + +/// Nibble-wise lookup of indices into a vector. +/// +/// The xperm4 instruction operates on nibbles. The rs1 register contains a vector of 8 +/// 4-bit elements. The rs2 register contains a vector of 8 4-bit indexes. The result is +/// each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 +/// is out of bounds. +/// +/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions +/// +/// Version: v1.0.1 +/// +/// Section: 3.48 +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +#[target_feature(enable = "zbkx")] +#[cfg_attr(test, assert_instr(xperm4))] +#[inline] +pub fn xperm4_32(rs1: u32, rs2: u32) -> u32 { + unsafe { _xperm4_32(rs1, rs2) } +} + +/// Carry-less multiply (high-part) +/// +/// clmulh produces the upper half of the 64-bit carry-less product. +/// +/// Source: RISC-V Bit-Manipulation ISA-extensions +/// +/// Version: v1.0.0 +/// +/// Section: 2.12 +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +#[target_feature(enable = "zbkc")] +#[cfg_attr(test, assert_instr(clmulh))] +#[inline] +pub fn clmulh_32(rs1: u32, rs2: u32) -> u32 { + unsafe { _clmulh_32(rs1, rs2) } +} + +/// Carry-less multiply (reversed) +/// +/// clmulr produces bits 62:31 of the 64-bit carry-less product. +/// +/// Source: RISC-V Bit-Manipulation ISA-extensions +/// +/// Version: v1.0.0 +/// +/// Section: 2.13 +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +#[target_feature(enable = "zbc")] +#[cfg_attr(test, assert_instr(clmulr))] +#[inline] +pub fn clmulr_32(rs1: u32, rs2: u32) -> u32 { + unsafe { _clmulr_32(rs1, rs2) } +} + +/// Place upper/lower halves of the source register into odd/even bits of the destination +/// respectivley. +/// +/// This instruction places bits in the low half of the source register into the even bit +/// positions of the destination, and bits in the high half of the source register into the odd +/// bit positions of the destination. It is the inverse of the unzip instruction. This +/// instruction is available only on RV32. +/// +/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions +/// +/// Version: v1.0.1 +/// +/// Section: 3.49 +#[target_feature(enable = "zbkb")] +// See #1464 +// #[cfg_attr(test, assert_instr(zip))] +#[inline] +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +pub fn zip_32(rs: u32) -> u32 { + unsafe { _zip_32(rs) } +} + +/// Place odd and even bits of the source word into upper/lower halves of the destination. +/// +/// This instruction places the even bits of the source register into the low half of the +/// destination, and the odd bits of the source into the high bits of the destination. It is +/// the inverse of the zip instruction. This instruction is available only on RV32. +/// +/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions +/// +/// Version: v1.0.1 +/// +/// Section: 3.45 +#[target_feature(enable = "zbkb")] +#[cfg_attr(test, assert_instr(unzip))] +#[inline] +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +pub fn unzip_32(rs: u32) -> u32 { + unsafe { _unzip_32(rs) } +} diff --git a/crates/core_arch/src/riscv32/zk.rs b/crates/core_arch/src/riscv32/zk.rs index 3ffe0819e7..34e5fb90a9 100644 --- a/crates/core_arch/src/riscv32/zk.rs +++ b/crates/core_arch/src/riscv32/zk.rs @@ -3,40 +3,34 @@ use stdarch_test::assert_instr; unsafe extern "llvm-intrinsic" { #[link_name = "llvm.riscv.aes32esi"] - fn _aes32esi(rs1: i32, rs2: i32, bs: i32) -> i32; + fn _aes32esi(rs1: u32, rs2: u32, bs: u32) -> u32; #[link_name = "llvm.riscv.aes32esmi"] - fn _aes32esmi(rs1: i32, rs2: i32, bs: i32) -> i32; + fn _aes32esmi(rs1: u32, rs2: u32, bs: u32) -> u32; #[link_name = "llvm.riscv.aes32dsi"] - fn _aes32dsi(rs1: i32, rs2: i32, bs: i32) -> i32; + fn _aes32dsi(rs1: u32, rs2: u32, bs: u32) -> u32; #[link_name = "llvm.riscv.aes32dsmi"] - fn _aes32dsmi(rs1: i32, rs2: i32, bs: i32) -> i32; - - #[link_name = "llvm.riscv.zip.i32"] - fn _zip(rs1: i32) -> i32; - - #[link_name = "llvm.riscv.unzip.i32"] - fn _unzip(rs1: i32) -> i32; + fn _aes32dsmi(rs1: u32, rs2: u32, bs: u32) -> u32; #[link_name = "llvm.riscv.sha512sig0h"] - fn _sha512sig0h(rs1: i32, rs2: i32) -> i32; + fn _sha512sig0h(rs1: u32, rs2: u32) -> u32; #[link_name = "llvm.riscv.sha512sig0l"] - fn _sha512sig0l(rs1: i32, rs2: i32) -> i32; + fn _sha512sig0l(rs1: u32, rs2: u32) -> u32; #[link_name = "llvm.riscv.sha512sig1h"] - fn _sha512sig1h(rs1: i32, rs2: i32) -> i32; + fn _sha512sig1h(rs1: u32, rs2: u32) -> u32; #[link_name = "llvm.riscv.sha512sig1l"] - fn _sha512sig1l(rs1: i32, rs2: i32) -> i32; + fn _sha512sig1l(rs1: u32, rs2: u32) -> u32; #[link_name = "llvm.riscv.sha512sum0r"] - fn _sha512sum0r(rs1: i32, rs2: i32) -> i32; + fn _sha512sum0r(rs1: u32, rs2: u32) -> u32; #[link_name = "llvm.riscv.sha512sum1r"] - fn _sha512sum1r(rs1: i32, rs2: i32) -> i32; + fn _sha512sum1r(rs1: u32, rs2: u32) -> u32; } /// AES final round encryption instruction for RV32. @@ -65,10 +59,10 @@ unsafe extern "llvm-intrinsic" { pub fn aes32esi(rs1: u32, rs2: u32) -> u32 { static_assert!(BS < 4); - unsafe { _aes32esi(rs1 as i32, rs2 as i32, BS as i32) as u32 } + unsafe { _aes32esi(rs1, rs2, BS as u32) } } -/// AES middle round encryption instruction for RV32 with. +/// AES middle round encryption instruction for RV32. /// /// This instruction sources a single byte from rs2 according to bs. To this it applies the /// forward AES SBox operation, and a partial forward MixColumn, before XOR’ing the result with @@ -94,7 +88,7 @@ pub fn aes32esi(rs1: u32, rs2: u32) -> u32 { pub fn aes32esmi(rs1: u32, rs2: u32) -> u32 { static_assert!(BS < 4); - unsafe { _aes32esmi(rs1 as i32, rs2 as i32, BS as i32) as u32 } + unsafe { _aes32esmi(rs1, rs2, BS as u32) } } /// AES final round decryption instruction for RV32. @@ -122,7 +116,7 @@ pub fn aes32esmi(rs1: u32, rs2: u32) -> u32 { pub fn aes32dsi(rs1: u32, rs2: u32) -> u32 { static_assert!(BS < 4); - unsafe { _aes32dsi(rs1 as i32, rs2 as i32, BS as i32) as u32 } + unsafe { _aes32dsi(rs1, rs2, BS as u32) } } /// AES middle round decryption instruction for RV32. @@ -151,48 +145,7 @@ pub fn aes32dsi(rs1: u32, rs2: u32) -> u32 { pub fn aes32dsmi(rs1: u32, rs2: u32) -> u32 { static_assert!(BS < 4); - unsafe { _aes32dsmi(rs1 as i32, rs2 as i32, BS as i32) as u32 } -} - -/// Place upper/lower halves of the source register into odd/even bits of the destination -/// respectivley. -/// -/// This instruction places bits in the low half of the source register into the even bit -/// positions of the destination, and bits in the high half of the source register into the odd -/// bit positions of the destination. It is the inverse of the unzip instruction. This -/// instruction is available only on RV32. -/// -/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions -/// -/// Version: v1.0.1 -/// -/// Section: 3.49 -#[target_feature(enable = "zbkb")] -// See #1464 -// #[cfg_attr(test, assert_instr(zip))] -#[inline] -#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] -pub fn zip(rs: u32) -> u32 { - unsafe { _zip(rs as i32) as u32 } -} - -/// Place odd and even bits of the source word into upper/lower halves of the destination. -/// -/// This instruction places the even bits of the source register into the low half of the -/// destination, and the odd bits of the source into the high bits of the destination. It is -/// the inverse of the zip instruction. This instruction is available only on RV32. -/// -/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions -/// -/// Version: v1.0.1 -/// -/// Section: 3.45 -#[target_feature(enable = "zbkb")] -#[cfg_attr(test, assert_instr(unzip))] -#[inline] -#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] -pub fn unzip(rs: u32) -> u32 { - unsafe { _unzip(rs as i32) as u32 } + unsafe { _aes32dsmi(rs1, rs2, BS as u32) } } /// Implements the high half of the Sigma0 transformation, as used in the SHA2-512 hash @@ -215,7 +168,7 @@ pub fn unzip(rs: u32) -> u32 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn sha512sig0h(rs1: u32, rs2: u32) -> u32 { - unsafe { _sha512sig0h(rs1 as i32, rs2 as i32) as u32 } + unsafe { _sha512sig0h(rs1, rs2) } } /// Implements the low half of the Sigma0 transformation, as used in the SHA2-512 hash function @@ -238,7 +191,7 @@ pub fn sha512sig0h(rs1: u32, rs2: u32) -> u32 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn sha512sig0l(rs1: u32, rs2: u32) -> u32 { - unsafe { _sha512sig0l(rs1 as i32, rs2 as i32) as u32 } + unsafe { _sha512sig0l(rs1, rs2) } } /// Implements the high half of the Sigma1 transformation, as used in the SHA2-512 hash @@ -261,7 +214,7 @@ pub fn sha512sig0l(rs1: u32, rs2: u32) -> u32 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn sha512sig1h(rs1: u32, rs2: u32) -> u32 { - unsafe { _sha512sig1h(rs1 as i32, rs2 as i32) as u32 } + unsafe { _sha512sig1h(rs1, rs2) } } /// Implements the low half of the Sigma1 transformation, as used in the SHA2-512 hash function @@ -283,7 +236,7 @@ pub fn sha512sig1h(rs1: u32, rs2: u32) -> u32 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn sha512sig1l(rs1: u32, rs2: u32) -> u32 { - unsafe { _sha512sig1l(rs1 as i32, rs2 as i32) as u32 } + unsafe { _sha512sig1l(rs1, rs2) } } /// Implements the Sum0 transformation, as used in the SHA2-512 hash function \[49\] (Section @@ -305,7 +258,7 @@ pub fn sha512sig1l(rs1: u32, rs2: u32) -> u32 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn sha512sum0r(rs1: u32, rs2: u32) -> u32 { - unsafe { _sha512sum0r(rs1 as i32, rs2 as i32) as u32 } + unsafe { _sha512sum0r(rs1, rs2) } } /// Implements the Sum1 transformation, as used in the SHA2-512 hash function \[49\] (Section @@ -327,5 +280,5 @@ pub fn sha512sum0r(rs1: u32, rs2: u32) -> u32 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn sha512sum1r(rs1: u32, rs2: u32) -> u32 { - unsafe { _sha512sum1r(rs1 as i32, rs2 as i32) as u32 } + unsafe { _sha512sum1r(rs1, rs2) } } diff --git a/crates/core_arch/src/riscv64/mod.rs b/crates/core_arch/src/riscv64/mod.rs index a7efc0c7f5..8301ea2b23 100644 --- a/crates/core_arch/src/riscv64/mod.rs +++ b/crates/core_arch/src/riscv64/mod.rs @@ -1,8 +1,12 @@ //! RISC-V RV64 specific intrinsics use crate::arch::asm; +mod zb; mod zk; +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +pub use zb::*; + #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub use zk::*; diff --git a/crates/core_arch/src/riscv64/zb.rs b/crates/core_arch/src/riscv64/zb.rs new file mode 100644 index 0000000000..95c6fdf9cd --- /dev/null +++ b/crates/core_arch/src/riscv64/zb.rs @@ -0,0 +1,132 @@ +#[cfg(test)] +use stdarch_test::assert_instr; + +unsafe extern "llvm-intrinsic" { + #[link_name = "llvm.riscv.xperm8.i64"] + fn _xperm8_64(rs1: u64, rs2: u64) -> u64; + + #[link_name = "llvm.riscv.xperm4.i64"] + fn _xperm4_64(rs1: u64, rs2: u64) -> u64; + + #[link_name = "llvm.riscv.orc.b.i64"] + fn _orc_b_64(rs: u64) -> u64; + + #[link_name = "llvm.riscv.clmul.i64"] + fn _clmul_64(rs1: u64, rs2: u64) -> u64; + + #[link_name = "llvm.riscv.clmulh.i64"] + fn _clmulh_64(rs1: u64, rs2: u64) -> u64; + + #[link_name = "llvm.riscv.clmulr.i64"] + fn _clmulr_64(rs1: u64, rs2: u64) -> u64; +} + +/// Byte-wise lookup of indices into a vector in registers. +/// +/// The xperm8 instruction operates on bytes. The rs1 register contains a vector of 8 +/// 8-bit elements. The rs2 register contains a vector of 8 8-bit indexes. The result is +/// each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 +/// is out of bounds. +/// +/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions +/// +/// Version: v1.0.1 +/// +/// Section: 3.47 +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +#[target_feature(enable = "zbkx")] +#[cfg_attr(test, assert_instr(xperm8))] +#[inline] +pub fn xperm8_64(rs1: u64, rs2: u64) -> u64 { + unsafe { _xperm8_64(rs1, rs2) } +} + +/// Nibble-wise lookup of indices into a vector. +/// +/// The xperm4 instruction operates on nibbles. The rs1 register contains a vector of 16 +/// 4-bit elements. The rs2 register contains a vector of 16 4-bit indexes. The result is +/// each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 +/// is out of bounds. +/// +/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions +/// +/// Version: v1.0.1 +/// +/// Section: 3.48 +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +#[target_feature(enable = "zbkx")] +#[cfg_attr(test, assert_instr(xperm4))] +#[inline] +pub fn xperm4_64(rs1: u64, rs2: u64) -> u64 { + unsafe { _xperm4_64(rs1, rs2) } +} + +/// Bitwise OR-Combine, byte granule +/// +/// Combines the bits within every byte through a reciprocal bitwise logical OR. This sets the bits of each byte in +/// the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the +/// respective byte of rs is set. +/// +/// Source: RISC-V Bit-Manipulation ISA-extensions +/// +/// Version: v1.0.0 +/// +/// Section: 2.24 +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +#[target_feature(enable = "zbb")] +#[cfg_attr(test, assert_instr(orc.b))] +#[inline] +pub fn orc_b_64(rs: u64) -> u64 { + unsafe { _orc_b_64(rs) } +} + +/// Carry-less multiply (low-part) +/// +/// clmul produces the lower half of the 128-bit carry-less product. +/// +/// Source: RISC-V Bit-Manipulation ISA-extensions +/// +/// Version: v1.0.0 +/// +/// Section: 2.11 +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +#[target_feature(enable = "zbkc")] +#[cfg_attr(test, assert_instr(clmul))] +#[inline] +pub fn clmul_64(rs1: u64, rs2: u64) -> u64 { + unsafe { _clmul_64(rs1, rs2) } +} + +/// Carry-less multiply (high-part) +/// +/// clmulh produces the upper half of the 128-bit carry-less product. +/// +/// Source: RISC-V Bit-Manipulation ISA-extensions +/// +/// Version: v1.0.0 +/// +/// Section: 2.12 +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +#[target_feature(enable = "zbkc")] +#[cfg_attr(test, assert_instr(clmulh))] +#[inline] +pub fn clmulh_64(rs1: u64, rs2: u64) -> u64 { + unsafe { _clmulh_64(rs1, rs2) } +} + +/// Carry-less multiply (reversed) +/// +/// clmulr produces bits 126:63 of the 128-bit carry-less product. +/// +/// Source: RISC-V Bit-Manipulation ISA-extensions +/// +/// Version: v1.0.0 +/// +/// Section: 2.13 +#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] +#[target_feature(enable = "zbc")] +#[cfg_attr(test, assert_instr(clmulr))] +#[inline] +pub fn clmulr_64(rs1: u64, rs2: u64) -> u64 { + unsafe { _clmulr_64(rs1, rs2) } +} diff --git a/crates/core_arch/src/riscv64/zk.rs b/crates/core_arch/src/riscv64/zk.rs index 21cfefafdd..ea5486b391 100644 --- a/crates/core_arch/src/riscv64/zk.rs +++ b/crates/core_arch/src/riscv64/zk.rs @@ -5,31 +5,31 @@ use crate::arch::asm; unsafe extern "llvm-intrinsic" { #[link_name = "llvm.riscv.aes64es"] - fn _aes64es(rs1: i64, rs2: i64) -> i64; + fn _aes64es(rs1: u64, rs2: u64) -> u64; #[link_name = "llvm.riscv.aes64esm"] - fn _aes64esm(rs1: i64, rs2: i64) -> i64; + fn _aes64esm(rs1: u64, rs2: u64) -> u64; #[link_name = "llvm.riscv.aes64ds"] - fn _aes64ds(rs1: i64, rs2: i64) -> i64; + fn _aes64ds(rs1: u64, rs2: u64) -> u64; #[link_name = "llvm.riscv.aes64dsm"] - fn _aes64dsm(rs1: i64, rs2: i64) -> i64; + fn _aes64dsm(rs1: u64, rs2: u64) -> u64; #[link_name = "llvm.riscv.aes64im"] - fn _aes64im(rs1: i64) -> i64; + fn _aes64im(rs1: u64) -> u64; #[link_name = "llvm.riscv.sha512sig0"] - fn _sha512sig0(rs1: i64) -> i64; + fn _sha512sig0(rs1: u64) -> u64; #[link_name = "llvm.riscv.sha512sig1"] - fn _sha512sig1(rs1: i64) -> i64; + fn _sha512sig1(rs1: u64) -> u64; #[link_name = "llvm.riscv.sha512sum0"] - fn _sha512sum0(rs1: i64) -> i64; + fn _sha512sum0(rs1: u64) -> u64; #[link_name = "llvm.riscv.sha512sum1"] - fn _sha512sum1(rs1: i64) -> i64; + fn _sha512sum1(rs1: u64) -> u64; } /// AES final round encryption instruction for RV64. @@ -49,7 +49,7 @@ unsafe extern "llvm-intrinsic" { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn aes64es(rs1: u64, rs2: u64) -> u64 { - unsafe { _aes64es(rs1 as i64, rs2 as i64) as u64 } + unsafe { _aes64es(rs1, rs2) } } /// AES middle round encryption instruction for RV64. @@ -69,7 +69,7 @@ pub fn aes64es(rs1: u64, rs2: u64) -> u64 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn aes64esm(rs1: u64, rs2: u64) -> u64 { - unsafe { _aes64esm(rs1 as i64, rs2 as i64) as u64 } + unsafe { _aes64esm(rs1, rs2) } } /// AES final round decryption instruction for RV64. @@ -89,7 +89,7 @@ pub fn aes64esm(rs1: u64, rs2: u64) -> u64 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn aes64ds(rs1: u64, rs2: u64) -> u64 { - unsafe { _aes64ds(rs1 as i64, rs2 as i64) as u64 } + unsafe { _aes64ds(rs1, rs2) } } /// AES middle round decryption instruction for RV64. @@ -109,7 +109,7 @@ pub fn aes64ds(rs1: u64, rs2: u64) -> u64 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn aes64dsm(rs1: u64, rs2: u64) -> u64 { - unsafe { _aes64dsm(rs1 as i64, rs2 as i64) as u64 } + unsafe { _aes64dsm(rs1, rs2) } } /// This instruction implements part of the KeySchedule operation for the AES Block cipher @@ -200,7 +200,7 @@ pub fn aes64ks2(rs1: u64, rs2: u64) -> u64 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn aes64im(rs1: u64) -> u64 { - unsafe { _aes64im(rs1 as i64) as u64 } + unsafe { _aes64im(rs1) } } /// Implements the Sigma0 transformation function as used in the SHA2-512 hash function \[49\] @@ -220,7 +220,7 @@ pub fn aes64im(rs1: u64) -> u64 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn sha512sig0(rs1: u64) -> u64 { - unsafe { _sha512sig0(rs1 as i64) as u64 } + unsafe { _sha512sig0(rs1) } } /// Implements the Sigma1 transformation function as used in the SHA2-512 hash function \[49\] @@ -240,7 +240,7 @@ pub fn sha512sig0(rs1: u64) -> u64 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn sha512sig1(rs1: u64) -> u64 { - unsafe { _sha512sig1(rs1 as i64) as u64 } + unsafe { _sha512sig1(rs1) } } /// Implements the Sum0 transformation function as used in the SHA2-512 hash function \[49\] @@ -260,7 +260,7 @@ pub fn sha512sig1(rs1: u64) -> u64 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn sha512sum0(rs1: u64) -> u64 { - unsafe { _sha512sum0(rs1 as i64) as u64 } + unsafe { _sha512sum0(rs1) } } /// Implements the Sum1 transformation function as used in the SHA2-512 hash function \[49\] @@ -280,5 +280,5 @@ pub fn sha512sum0(rs1: u64) -> u64 { #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn sha512sum1(rs1: u64) -> u64 { - unsafe { _sha512sum1(rs1 as i64) as u64 } + unsafe { _sha512sum1(rs1) } } diff --git a/crates/core_arch/src/riscv_shared/zb.rs b/crates/core_arch/src/riscv_shared/zb.rs index 79ffe2af33..04a42f0235 100644 --- a/crates/core_arch/src/riscv_shared/zb.rs +++ b/crates/core_arch/src/riscv_shared/zb.rs @@ -1,34 +1,12 @@ #[cfg(test)] use stdarch_test::assert_instr; -#[cfg(target_arch = "riscv32")] unsafe extern "llvm-intrinsic" { #[link_name = "llvm.riscv.orc.b.i32"] - fn _orc_b_32(rs: i32) -> i32; + fn _orc_b_32(rs: u32) -> u32; #[link_name = "llvm.riscv.clmul.i32"] - fn _clmul_32(rs1: i32, rs2: i32) -> i32; - - #[link_name = "llvm.riscv.clmulh.i32"] - fn _clmulh_32(rs1: i32, rs2: i32) -> i32; - - #[link_name = "llvm.riscv.clmulr.i32"] - fn _clmulr_32(rs1: i32, rs2: i32) -> i32; -} - -#[cfg(target_arch = "riscv64")] -unsafe extern "llvm-intrinsic" { - #[link_name = "llvm.riscv.orc.b.i64"] - fn _orc_b_64(rs1: i64) -> i64; - - #[link_name = "llvm.riscv.clmul.i64"] - fn _clmul_64(rs1: i64, rs2: i64) -> i64; - - #[link_name = "llvm.riscv.clmulh.i64"] - fn _clmulh_64(rs1: i64, rs2: i64) -> i64; - - #[link_name = "llvm.riscv.clmulr.i64"] - fn _clmulr_64(rs1: i64, rs2: i64) -> i64; + fn _clmul_32(rs1: u32, rs2: u32) -> u32; } /// Bitwise OR-Combine, byte granule @@ -46,21 +24,13 @@ unsafe extern "llvm-intrinsic" { #[target_feature(enable = "zbb")] #[cfg_attr(test, assert_instr(orc.b))] #[inline] -pub fn orc_b(rs: usize) -> usize { - #[cfg(target_arch = "riscv32")] - unsafe { - _orc_b_32(rs as i32) as usize - } - - #[cfg(target_arch = "riscv64")] - unsafe { - _orc_b_64(rs as i64) as usize - } +pub fn orc_b_32(rs: u32) -> u32 { + unsafe { _orc_b_32(rs) } } /// Carry-less multiply (low-part) /// -/// clmul produces the lower half of the 2·XLEN carry-less product. +/// clmul produces the lower half of the 32-bit carry-less product. /// /// Source: RISC-V Bit-Manipulation ISA-extensions /// @@ -71,64 +41,6 @@ pub fn orc_b(rs: usize) -> usize { #[target_feature(enable = "zbkc")] #[cfg_attr(test, assert_instr(clmul))] #[inline] -pub fn clmul(rs1: usize, rs2: usize) -> usize { - #[cfg(target_arch = "riscv32")] - unsafe { - _clmul_32(rs1 as i32, rs2 as i32) as usize - } - - #[cfg(target_arch = "riscv64")] - unsafe { - _clmul_64(rs1 as i64, rs2 as i64) as usize - } -} - -/// Carry-less multiply (high-part) -/// -/// clmulh produces the upper half of the 2·XLEN carry-less product. -/// -/// Source: RISC-V Bit-Manipulation ISA-extensions -/// -/// Version: v1.0.0 -/// -/// Section: 2.12 -#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] -#[target_feature(enable = "zbkc")] -#[cfg_attr(test, assert_instr(clmulh))] -#[inline] -pub fn clmulh(rs1: usize, rs2: usize) -> usize { - #[cfg(target_arch = "riscv32")] - unsafe { - _clmulh_32(rs1 as i32, rs2 as i32) as usize - } - - #[cfg(target_arch = "riscv64")] - unsafe { - _clmulh_64(rs1 as i64, rs2 as i64) as usize - } -} - -/// Carry-less multiply (reversed) -/// -/// clmulr produces bits 2·XLEN−2:XLEN-1 of the 2·XLEN carry-less product. -/// -/// Source: RISC-V Bit-Manipulation ISA-extensions -/// -/// Version: v1.0.0 -/// -/// Section: 2.13 -#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] -#[target_feature(enable = "zbc")] -#[cfg_attr(test, assert_instr(clmulr))] -#[inline] -pub fn clmulr(rs1: usize, rs2: usize) -> usize { - #[cfg(target_arch = "riscv32")] - unsafe { - _clmulr_32(rs1 as i32, rs2 as i32) as usize - } - - #[cfg(target_arch = "riscv64")] - unsafe { - _clmulr_64(rs1 as i64, rs2 as i64) as usize - } +pub fn clmul_32(rs1: u32, rs2: u32) -> u32 { + unsafe { _clmul_32(rs1, rs2) } } diff --git a/crates/core_arch/src/riscv_shared/zk.rs b/crates/core_arch/src/riscv_shared/zk.rs index 589ea97798..6966686731 100644 --- a/crates/core_arch/src/riscv_shared/zk.rs +++ b/crates/core_arch/src/riscv_shared/zk.rs @@ -3,102 +3,28 @@ use stdarch_test::assert_instr; unsafe extern "llvm-intrinsic" { #[link_name = "llvm.riscv.sm4ed"] - fn _sm4ed(rs1: i32, rs2: i32, bs: i32) -> i32; + fn _sm4ed(rs1: u32, rs2: u32, bs: u32) -> u32; #[link_name = "llvm.riscv.sm4ks"] - fn _sm4ks(rs1: i32, rs2: i32, bs: i32) -> i32; + fn _sm4ks(rs1: u32, rs2: u32, bs: u32) -> u32; #[link_name = "llvm.riscv.sm3p0"] - fn _sm3p0(rs1: i32) -> i32; + fn _sm3p0(rs1: u32) -> u32; #[link_name = "llvm.riscv.sm3p1"] - fn _sm3p1(rs1: i32) -> i32; + fn _sm3p1(rs1: u32) -> u32; #[link_name = "llvm.riscv.sha256sig0"] - fn _sha256sig0(rs1: i32) -> i32; + fn _sha256sig0(rs1: u32) -> u32; #[link_name = "llvm.riscv.sha256sig1"] - fn _sha256sig1(rs1: i32) -> i32; + fn _sha256sig1(rs1: u32) -> u32; #[link_name = "llvm.riscv.sha256sum0"] - fn _sha256sum0(rs1: i32) -> i32; + fn _sha256sum0(rs1: u32) -> u32; #[link_name = "llvm.riscv.sha256sum1"] - fn _sha256sum1(rs1: i32) -> i32; -} - -#[cfg(target_arch = "riscv32")] -unsafe extern "llvm-intrinsic" { - #[link_name = "llvm.riscv.xperm8.i32"] - fn _xperm8_32(rs1: i32, rs2: i32) -> i32; - - #[link_name = "llvm.riscv.xperm4.i32"] - fn _xperm4_32(rs1: i32, rs2: i32) -> i32; -} - -#[cfg(target_arch = "riscv64")] -unsafe extern "llvm-intrinsic" { - #[link_name = "llvm.riscv.xperm8.i64"] - fn _xperm8_64(rs1: i64, rs2: i64) -> i64; - - #[link_name = "llvm.riscv.xperm4.i64"] - fn _xperm4_64(rs1: i64, rs2: i64) -> i64; -} - -/// Byte-wise lookup of indicies into a vector in registers. -/// -/// The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8 -/// 8-bit elements. The rs2 register contains a vector of XLEN/8 8-bit indexes. The result is -/// each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 -/// is out of bounds. -/// -/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions -/// -/// Version: v1.0.1 -/// -/// Section: 3.47 -#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] -#[target_feature(enable = "zbkx")] -#[cfg_attr(test, assert_instr(xperm8))] -#[inline] -pub fn xperm8(rs1: usize, rs2: usize) -> usize { - #[cfg(target_arch = "riscv32")] - unsafe { - _xperm8_32(rs1 as i32, rs2 as i32) as usize - } - - #[cfg(target_arch = "riscv64")] - unsafe { - _xperm8_64(rs1 as i64, rs2 as i64) as usize - } -} - -/// Nibble-wise lookup of indicies into a vector. -/// -/// The xperm4 instruction operates on nibbles. The rs1 register contains a vector of XLEN/4 -/// 4-bit elements. The rs2 register contains a vector of XLEN/4 4-bit indexes. The result is -/// each element in rs2 replaced by the indexed element in rs1, or zero if the index into rs2 -/// is out of bounds. -/// -/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions -/// -/// Version: v1.0.1 -/// -/// Section: 3.48 -#[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] -#[target_feature(enable = "zbkx")] -#[cfg_attr(test, assert_instr(xperm4))] -#[inline] -pub fn xperm4(rs1: usize, rs2: usize) -> usize { - #[cfg(target_arch = "riscv32")] - unsafe { - _xperm4_32(rs1 as i32, rs2 as i32) as usize - } - - #[cfg(target_arch = "riscv64")] - unsafe { - _xperm4_64(rs1 as i64, rs2 as i64) as usize - } + fn _sha256sum1(rs1: u32) -> u32; } /// Implements the Sigma0 transformation function as used in the SHA2-256 hash function \[49\] @@ -121,7 +47,7 @@ pub fn xperm4(rs1: usize, rs2: usize) -> usize { #[cfg_attr(test, assert_instr(sha256sig0))] #[inline] pub fn sha256sig0(rs1: u32) -> u32 { - unsafe { _sha256sig0(rs1 as i32) as u32 } + unsafe { _sha256sig0(rs1) } } /// Implements the Sigma1 transformation function as used in the SHA2-256 hash function \[49\] @@ -144,7 +70,7 @@ pub fn sha256sig0(rs1: u32) -> u32 { #[cfg_attr(test, assert_instr(sha256sig1))] #[inline] pub fn sha256sig1(rs1: u32) -> u32 { - unsafe { _sha256sig1(rs1 as i32) as u32 } + unsafe { _sha256sig1(rs1) } } /// Implements the Sum0 transformation function as used in the SHA2-256 hash function \[49\] @@ -167,7 +93,7 @@ pub fn sha256sig1(rs1: u32) -> u32 { #[cfg_attr(test, assert_instr(sha256sum0))] #[inline] pub fn sha256sum0(rs1: u32) -> u32 { - unsafe { _sha256sum0(rs1 as i32) as u32 } + unsafe { _sha256sum0(rs1) } } /// Implements the Sum1 transformation function as used in the SHA2-256 hash function \[49\] @@ -190,7 +116,7 @@ pub fn sha256sum0(rs1: u32) -> u32 { #[cfg_attr(test, assert_instr(sha256sum1))] #[inline] pub fn sha256sum1(rs1: u32) -> u32 { - unsafe { _sha256sum1(rs1 as i32) as u32 } + unsafe { _sha256sum1(rs1) } } /// Accelerates the block encrypt/decrypt operation of the SM4 block cipher \[5, 31\]. @@ -266,7 +192,7 @@ pub fn sha256sum1(rs1: u32) -> u32 { pub fn sm4ed(rs1: u32, rs2: u32) -> u32 { static_assert!(BS < 4); - unsafe { _sm4ed(rs1 as i32, rs2 as i32, BS as i32) as u32 } + unsafe { _sm4ed(rs1, rs2, BS as u32) } } /// Accelerates the Key Schedule operation of the SM4 block cipher \[5, 31\] with `bs=0`. @@ -342,7 +268,7 @@ pub fn sm4ed(rs1: u32, rs2: u32) -> u32 { pub fn sm4ks(rs1: u32, rs2: u32) -> u32 { static_assert!(BS < 4); - unsafe { _sm4ks(rs1 as i32, rs2 as i32, BS as i32) as u32 } + unsafe { _sm4ks(rs1, rs2, BS as u32) } } /// Implements the P0 transformation function as used in the SM3 hash function [4, 30]. @@ -377,7 +303,7 @@ pub fn sm4ks(rs1: u32, rs2: u32) -> u32 { #[cfg_attr(test, assert_instr(sm3p0))] #[inline] pub fn sm3p0(rs1: u32) -> u32 { - unsafe { _sm3p0(rs1 as i32) as u32 } + unsafe { _sm3p0(rs1) } } /// Implements the P1 transformation function as used in the SM3 hash function [4, 30]. @@ -418,5 +344,5 @@ pub fn sm3p0(rs1: u32) -> u32 { #[cfg_attr(test, assert_instr(sm3p1))] #[inline] pub fn sm3p1(rs1: u32) -> u32 { - unsafe { _sm3p1(rs1 as i32) as u32 } + unsafe { _sm3p1(rs1) } }