From 7ffdf59bb584aba3a20cbcbd2146fa9408e8f787 Mon Sep 17 00:00:00 2001 From: TechnoPorg Date: Mon, 12 Oct 2026 09:11:54 -0400 Subject: [PATCH] cleanup: remove rustc_legacy_const_generics from unstable intrinsics --- crates/core_arch/src/hexagon/scalar.rs | 160 ----------------------- crates/core_arch/src/mips/msa.rs | 140 -------------------- crates/core_arch/src/powerpc/vsx.rs | 1 - crates/core_arch/src/riscv32/zk.rs | 4 - crates/core_arch/src/riscv64/zk.rs | 1 - crates/core_arch/src/riscv_shared/zk.rs | 20 ++- crates/stdarch-gen-hexagon/src/scalar.rs | 11 -- crates/stdarch-verify/src/lib.rs | 30 +---- crates/stdarch-verify/tests/arm.rs | 10 +- crates/stdarch-verify/tests/mips.rs | 48 ++++--- crates/stdarch-verify/tests/x86-intel.rs | 4 +- 11 files changed, 53 insertions(+), 376 deletions(-) diff --git a/crates/core_arch/src/hexagon/scalar.rs b/crates/core_arch/src/hexagon/scalar.rs index 42429a9590..5772fd41ef 100644 --- a/crates/core_arch/src/hexagon/scalar.rs +++ b/crates/core_arch/src/hexagon/scalar.rs @@ -2021,7 +2021,6 @@ pub unsafe fn Q6_R_add_RlRl_sat(rt: i32, rs: i32) -> i32 { /// Instruction Type: ALU32_ADDI /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(add, IS16 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_add_RI(rs: i32) -> i32 { @@ -2089,7 +2088,6 @@ pub unsafe fn Q6_R_and_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(and, IS10 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_and_RI(rs: i32) -> i32 { @@ -2179,7 +2177,6 @@ pub unsafe fn Q6_R_combine_RlRl(rt: i32, rs: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(0, 1)] #[cfg_attr(test, assert_instr(combine, IS8 = 0, IS8_2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_combine_II() -> i64 { @@ -2358,7 +2355,6 @@ pub unsafe fn Q6_R_or_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(or, IS10 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_or_RI(rs: i32) -> i32 { @@ -2602,7 +2598,6 @@ pub unsafe fn Q6_P_sub_PP(rtt: i64, rss: i64) -> i64 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(0)] #[cfg_attr(test, assert_instr(sub, IS10 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_sub_IR(rs: i32) -> i32 { @@ -2779,7 +2774,6 @@ pub unsafe fn Q6_R_equals_R(rs: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_Rh_equals_I(rx: i32) -> i32 { static_assert_uimm_bits!(IU16, 16); @@ -2791,7 +2785,6 @@ pub unsafe fn Q6_Rh_equals_I(rx: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_Rl_equals_I(rx: i32) -> i32 { static_assert_uimm_bits!(IU16, 16); @@ -2813,7 +2806,6 @@ pub unsafe fn Q6_P_equals_P(rss: i64) -> i64 { /// Instruction Type: ALU64 /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_equals_I() -> i64 { static_assert_simm_bits!(IS8, 8); @@ -2825,7 +2817,6 @@ pub unsafe fn Q6_P_equals_I() -> i64 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_equals_I() -> i32 { static_assert_simm_bits!(IS16, 16); @@ -3607,7 +3598,6 @@ pub unsafe fn Q6_P_bitsplit_RR(rs: i32, rt: i32) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(bitsplit, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_bitsplit_RI(rs: i32) -> i64 { @@ -3642,7 +3632,6 @@ pub unsafe fn Q6_p_cmpb_eq_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cmpb, IU8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_cmpb_eq_RI(rs: i32) -> i32 { @@ -3666,7 +3655,6 @@ pub unsafe fn Q6_p_cmpb_gt_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cmpb, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_cmpb_gt_RI(rs: i32) -> i32 { @@ -3690,7 +3678,6 @@ pub unsafe fn Q6_p_cmpb_gtu_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cmpb, IU7 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_cmpb_gtu_RI(rs: i32) -> i32 { @@ -3714,7 +3701,6 @@ pub unsafe fn Q6_p_cmph_eq_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cmph, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_cmph_eq_RI(rs: i32) -> i32 { @@ -3738,7 +3724,6 @@ pub unsafe fn Q6_p_cmph_gt_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cmph, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_cmph_gt_RI(rs: i32) -> i32 { @@ -3762,7 +3747,6 @@ pub unsafe fn Q6_p_cmph_gtu_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cmph, IU7 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_cmph_gtu_RI(rs: i32) -> i32 { @@ -3775,7 +3759,6 @@ pub unsafe fn Q6_p_cmph_gtu_RI(rs: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(0)] #[cfg_attr(test, assert_instr(combine, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_combine_IR(rs: i32) -> i64 { @@ -3788,7 +3771,6 @@ pub unsafe fn Q6_P_combine_IR(rs: i32) -> i64 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(combine, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_combine_RI(rs: i32) -> i64 { @@ -3801,7 +3783,6 @@ pub unsafe fn Q6_P_combine_RI(rs: i32) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cround, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_cround_RI(rs: i32) -> i32 { @@ -3869,7 +3850,6 @@ pub unsafe fn Q6_R_cmp_eq_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cmp, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_cmp_eq_RI(rs: i32) -> i32 { @@ -3892,7 +3872,6 @@ pub unsafe fn Q6_R_not_cmp_eq_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_not_cmp_eq_RI(rs: i32) -> i32 { static_assert_simm_bits!(IS8, 8); @@ -3904,7 +3883,6 @@ pub unsafe fn Q6_R_not_cmp_eq_RI(rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(round, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_round_RI(rs: i32) -> i32 { @@ -3917,7 +3895,6 @@ pub unsafe fn Q6_R_round_RI(rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(round, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_round_RI_sat(rs: i32) -> i32 { @@ -3974,7 +3951,6 @@ pub unsafe fn Q6_p_any8_vcmpb_eq_PP(rss: i64, rtt: i64) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vcmpb, IU8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_vcmpb_eq_PI(rss: i64) -> i32 { @@ -3998,7 +3974,6 @@ pub unsafe fn Q6_p_vcmpb_gt_PP(rss: i64, rtt: i64) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vcmpb, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_vcmpb_gt_PI(rss: i64) -> i32 { @@ -4011,7 +3986,6 @@ pub unsafe fn Q6_p_vcmpb_gt_PI(rss: i64) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vcmpb, IU7 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_vcmpb_gtu_PI(rss: i64) -> i32 { @@ -4024,7 +3998,6 @@ pub unsafe fn Q6_p_vcmpb_gtu_PI(rss: i64) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vcmph, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_vcmph_eq_PI(rss: i64) -> i32 { @@ -4037,7 +4010,6 @@ pub unsafe fn Q6_p_vcmph_eq_PI(rss: i64) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vcmph, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_vcmph_gt_PI(rss: i64) -> i32 { @@ -4050,7 +4022,6 @@ pub unsafe fn Q6_p_vcmph_gt_PI(rss: i64) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vcmph, IU7 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_vcmph_gtu_PI(rss: i64) -> i32 { @@ -4063,7 +4034,6 @@ pub unsafe fn Q6_p_vcmph_gtu_PI(rss: i64) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vcmpw, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_vcmpw_eq_PI(rss: i64) -> i32 { @@ -4076,7 +4046,6 @@ pub unsafe fn Q6_p_vcmpw_eq_PI(rss: i64) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vcmpw, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_vcmpw_gt_PI(rss: i64) -> i32 { @@ -4089,7 +4058,6 @@ pub unsafe fn Q6_p_vcmpw_gt_PI(rss: i64) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vcmpw, IU7 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_vcmpw_gtu_PI(rss: i64) -> i32 { @@ -4256,7 +4224,6 @@ pub unsafe fn Q6_p_bitsclr_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(bitsclr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_bitsclr_RI(rs: i32) -> i32 { @@ -4291,7 +4258,6 @@ pub unsafe fn Q6_p_cmp_eq_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cmp, IS10 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_cmp_eq_RI(rs: i32) -> i32 { @@ -4315,7 +4281,6 @@ pub unsafe fn Q6_p_cmp_eq_PP(rss: i64, rtt: i64) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cmp, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_cmp_ge_RI(rs: i32) -> i32 { @@ -4328,7 +4293,6 @@ pub unsafe fn Q6_p_cmp_ge_RI(rs: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cmp, IU8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_cmp_geu_RI(rs: i32) -> i32 { @@ -4352,7 +4316,6 @@ pub unsafe fn Q6_p_cmp_gt_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cmp, IS10 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_cmp_gt_RI(rs: i32) -> i32 { @@ -4387,7 +4350,6 @@ pub unsafe fn Q6_p_cmp_gtu_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cmp, IU9 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_cmp_gtu_RI(rs: i32) -> i32 { @@ -4455,7 +4417,6 @@ pub unsafe fn Q6_R_mux_pRR(pu: i32, rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1, 2)] #[cfg_attr(test, assert_instr(mux, IS8 = 0, IS8_2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_mux_pII(pu: i32) -> i32 { @@ -4469,7 +4430,6 @@ pub unsafe fn Q6_R_mux_pII(pu: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(mux, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_mux_pRI(pu: i32, rs: i32) -> i32 { @@ -4482,7 +4442,6 @@ pub unsafe fn Q6_R_mux_pRI(pu: i32, rs: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(mux, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_mux_pIR(pu: i32, rs: i32) -> i32 { @@ -4645,7 +4604,6 @@ pub unsafe fn Q6_p_not_cmp_gt_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_not_cmp_gt_RI(rs: i32) -> i32 { static_assert_simm_bits!(IS10, 10); @@ -4667,7 +4625,6 @@ pub unsafe fn Q6_p_not_cmp_gtu_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_not_cmp_gtu_RI(rs: i32) -> i32 { static_assert_uimm_bits!(IU9, 9); @@ -4689,7 +4646,6 @@ pub unsafe fn Q6_p_not_cmp_eq_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU32_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_not_cmp_eq_RI(rs: i32) -> i32 { static_assert_simm_bits!(IS10, 10); @@ -4732,7 +4688,6 @@ pub unsafe fn Q6_p_not_bitsclr_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_not_bitsclr_RI(rs: i32) -> i32 { static_assert_uimm_bits!(IU6, 6); @@ -5084,7 +5039,6 @@ pub unsafe fn Q6_R_convert_w2sf_R(rs: i32) -> f32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(dfclass, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_dfclass_PI(rss: f64) -> i32 { @@ -5141,7 +5095,6 @@ pub unsafe fn Q6_p_dfcmp_uo_PP(rss: f64, rtt: f64) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0)] #[cfg_attr(test, assert_instr(dfmake, IU10 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_dfmake_I_neg() -> f64 { @@ -5154,7 +5107,6 @@ pub unsafe fn Q6_P_dfmake_I_neg() -> f64 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0)] #[cfg_attr(test, assert_instr(dfmake, IU10 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_dfmake_I_pos() -> f64 { @@ -5178,7 +5130,6 @@ pub unsafe fn Q6_R_sfadd_RR(rs: f32, rt: f32) -> f32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(sfclass, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_sfclass_RI(rs: f32) -> i32 { @@ -5323,7 +5274,6 @@ pub unsafe fn Q6_R_sfmpynac_RR_lib(rx: f32, rs: f32, rt: f32) -> f32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0)] #[cfg_attr(test, assert_instr(sfmake, IU10 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_sfmake_I_neg() -> f32 { @@ -5336,7 +5286,6 @@ pub unsafe fn Q6_R_sfmake_I_neg() -> f32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0)] #[cfg_attr(test, assert_instr(sfmake, IU10 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_sfmake_I_pos() -> f32 { @@ -5404,7 +5353,6 @@ pub unsafe fn Q6_R_addacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { /// Instruction Type: M /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(add, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_addacc_RI(rx: i32, rs: i32) -> i32 { @@ -5769,7 +5717,6 @@ pub unsafe fn Q6_R_mpyiacc_RR(rx: i32, rs: i32, rt: i32) -> i32 { /// Instruction Type: M /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(mpyi, IU8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_mpyinac_RI(rx: i32, rs: i32) -> i32 { @@ -5782,7 +5729,6 @@ pub unsafe fn Q6_R_mpyinac_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: M /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(mpyi, IU8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_mpyiacc_RI(rx: i32, rs: i32) -> i32 { @@ -7830,7 +7776,6 @@ pub unsafe fn Q6_R_addnac_RR(rx: i32, rs: i32, rt: i32) -> i32 { /// Instruction Type: M /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(add, IS8 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_addnac_RI(rx: i32, rs: i32) -> i32 { @@ -8459,7 +8404,6 @@ pub unsafe fn Q6_R_mpyacc_RR_s1_sat(rx: i32, rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0, 2)] #[cfg_attr(test, assert_instr(add, IU6 = 0, IU6_2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_add_mpyi_IRI(rs: i32) -> i32 { @@ -8473,7 +8417,6 @@ pub unsafe fn Q6_R_add_mpyi_IRI(rs: i32) -> i3 /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(add, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_add_mpyi_RRI(ru: i32, rs: i32) -> i32 { @@ -8486,7 +8429,6 @@ pub unsafe fn Q6_R_add_mpyi_RRI(ru: i32, rs: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(add, IU6_2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_add_mpyi_RIR(ru: i32, rs: i32) -> i32 { @@ -8499,7 +8441,6 @@ pub unsafe fn Q6_R_add_mpyi_RIR(ru: i32, rs: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0)] #[cfg_attr(test, assert_instr(add, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_add_mpyi_IRR(rs: i32, rt: i32) -> i32 { @@ -8864,7 +8805,6 @@ pub unsafe fn Q6_P_vrmpybu_PP(rss: i64, rtt: i64) -> i64 { /// Instruction Type: S_3op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(addasl, IU3 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_addasl_RRI(rt: i32, rs: i32) -> i32 { @@ -8877,7 +8817,6 @@ pub unsafe fn Q6_R_addasl_RRI(rt: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(asl, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_asl_PI(rss: i64) -> i64 { @@ -8890,7 +8829,6 @@ pub unsafe fn Q6_P_asl_PI(rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asl, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_aslacc_PI(rxx: i64, rss: i64) -> i64 { @@ -8903,7 +8841,6 @@ pub unsafe fn Q6_P_aslacc_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asl, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_asland_PI(rxx: i64, rss: i64) -> i64 { @@ -8916,7 +8853,6 @@ pub unsafe fn Q6_P_asland_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asl, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_aslnac_PI(rxx: i64, rss: i64) -> i64 { @@ -8929,7 +8865,6 @@ pub unsafe fn Q6_P_aslnac_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asl, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_aslor_PI(rxx: i64, rss: i64) -> i64 { @@ -8942,7 +8877,6 @@ pub unsafe fn Q6_P_aslor_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asl, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_aslxacc_PI(rxx: i64, rss: i64) -> i64 { @@ -8955,7 +8889,6 @@ pub unsafe fn Q6_P_aslxacc_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(asl, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_asl_RI(rs: i32) -> i32 { @@ -8968,7 +8901,6 @@ pub unsafe fn Q6_R_asl_RI(rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asl, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_aslacc_RI(rx: i32, rs: i32) -> i32 { @@ -8981,7 +8913,6 @@ pub unsafe fn Q6_R_aslacc_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asl, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_asland_RI(rx: i32, rs: i32) -> i32 { @@ -8994,7 +8925,6 @@ pub unsafe fn Q6_R_asland_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asl, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_aslnac_RI(rx: i32, rs: i32) -> i32 { @@ -9007,7 +8937,6 @@ pub unsafe fn Q6_R_aslnac_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asl, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_aslor_RI(rx: i32, rs: i32) -> i32 { @@ -9020,7 +8949,6 @@ pub unsafe fn Q6_R_aslor_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(asl, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_asl_RI_sat(rs: i32) -> i32 { @@ -9033,7 +8961,6 @@ pub unsafe fn Q6_R_asl_RI_sat(rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asl, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_aslxacc_RI(rx: i32, rs: i32) -> i32 { @@ -9046,7 +8973,6 @@ pub unsafe fn Q6_R_aslxacc_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vaslh, IU4 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_vaslh_PI(rss: i64) -> i64 { @@ -9059,7 +8985,6 @@ pub unsafe fn Q6_P_vaslh_PI(rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vaslw, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_vaslw_PI(rss: i64) -> i64 { @@ -9226,7 +9151,6 @@ pub unsafe fn Q6_P_vaslw_PR(rss: i64, rt: i32) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(asr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_asr_PI(rss: i64) -> i64 { @@ -9239,7 +9163,6 @@ pub unsafe fn Q6_P_asr_PI(rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_asracc_PI(rxx: i64, rss: i64) -> i64 { @@ -9252,7 +9175,6 @@ pub unsafe fn Q6_P_asracc_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_asrand_PI(rxx: i64, rss: i64) -> i64 { @@ -9265,7 +9187,6 @@ pub unsafe fn Q6_P_asrand_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_asrnac_PI(rxx: i64, rss: i64) -> i64 { @@ -9278,7 +9199,6 @@ pub unsafe fn Q6_P_asrnac_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_asror_PI(rxx: i64, rss: i64) -> i64 { @@ -9291,7 +9211,6 @@ pub unsafe fn Q6_P_asror_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(asr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_asr_PI_rnd(rss: i64) -> i64 { @@ -9304,7 +9223,6 @@ pub unsafe fn Q6_P_asr_PI_rnd(rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(asrrnd, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_asrrnd_PI(rss: i64) -> i64 { @@ -9317,7 +9235,6 @@ pub unsafe fn Q6_P_asrrnd_PI(rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(asr, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_asr_RI(rs: i32) -> i32 { @@ -9330,7 +9247,6 @@ pub unsafe fn Q6_R_asr_RI(rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asr, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_asracc_RI(rx: i32, rs: i32) -> i32 { @@ -9343,7 +9259,6 @@ pub unsafe fn Q6_R_asracc_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asr, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_asrand_RI(rx: i32, rs: i32) -> i32 { @@ -9356,7 +9271,6 @@ pub unsafe fn Q6_R_asrand_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asr, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_asrnac_RI(rx: i32, rs: i32) -> i32 { @@ -9369,7 +9283,6 @@ pub unsafe fn Q6_R_asrnac_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(asr, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_asror_RI(rx: i32, rs: i32) -> i32 { @@ -9382,7 +9295,6 @@ pub unsafe fn Q6_R_asror_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(asr, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_asr_RI_rnd(rs: i32) -> i32 { @@ -9395,7 +9307,6 @@ pub unsafe fn Q6_R_asr_RI_rnd(rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(asrrnd, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_asrrnd_RI(rs: i32) -> i32 { @@ -9408,7 +9319,6 @@ pub unsafe fn Q6_R_asrrnd_RI(rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vasrw, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_vasrw_PI(rss: i64) -> i32 { @@ -9421,7 +9331,6 @@ pub unsafe fn Q6_R_vasrw_PI(rss: i64) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vasrh, IU4 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_vasrh_PI(rss: i64) -> i64 { @@ -9434,7 +9343,6 @@ pub unsafe fn Q6_P_vasrh_PI(rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vasrw, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_vasrw_PI(rss: i64) -> i64 { @@ -9711,7 +9619,6 @@ pub unsafe fn Q6_R_clb_P(rss: i64) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(clrbit, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_clrbit_RI(rs: i32) -> i32 { @@ -9790,7 +9697,6 @@ pub unsafe fn Q6_P_deinterleave_P(rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1, 2)] #[cfg_attr(test, assert_instr(extractu, IU5 = 0, IU5_2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_extractu_RII(rs: i32) -> i32 { @@ -9815,7 +9721,6 @@ pub unsafe fn Q6_R_extractu_RP(rs: i32, rtt: i64) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1, 2)] #[cfg_attr(test, assert_instr(extractu, IU6 = 0, IU6_2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_extractu_PII(rss: i64) -> i64 { @@ -9840,7 +9745,6 @@ pub unsafe fn Q6_P_extractu_PP(rss: i64, rtt: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2, 3)] #[cfg_attr(test, assert_instr(insert, IU5 = 0, IU5_2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_insert_RII(rx: i32, rs: i32) -> i32 { @@ -9865,7 +9769,6 @@ pub unsafe fn Q6_R_insert_RP(rx: i32, rs: i32, rtt: i64) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2, 3)] #[cfg_attr(test, assert_instr(insert, IU6 = 0, IU6_2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_insert_PII(rxx: i64, rss: i64) -> i64 { @@ -10055,7 +9958,6 @@ pub unsafe fn Q6_P_vlslw_PR(rss: i64, rt: i32) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(lsr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_lsr_PI(rss: i64) -> i64 { @@ -10068,7 +9970,6 @@ pub unsafe fn Q6_P_lsr_PI(rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(lsr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_lsracc_PI(rxx: i64, rss: i64) -> i64 { @@ -10081,7 +9982,6 @@ pub unsafe fn Q6_P_lsracc_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(lsr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_lsrand_PI(rxx: i64, rss: i64) -> i64 { @@ -10094,7 +9994,6 @@ pub unsafe fn Q6_P_lsrand_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(lsr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_lsrnac_PI(rxx: i64, rss: i64) -> i64 { @@ -10107,7 +10006,6 @@ pub unsafe fn Q6_P_lsrnac_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(lsr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_lsror_PI(rxx: i64, rss: i64) -> i64 { @@ -10120,7 +10018,6 @@ pub unsafe fn Q6_P_lsror_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(lsr, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_lsrxacc_PI(rxx: i64, rss: i64) -> i64 { @@ -10133,7 +10030,6 @@ pub unsafe fn Q6_P_lsrxacc_PI(rxx: i64, rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(lsr, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_lsr_RI(rs: i32) -> i32 { @@ -10146,7 +10042,6 @@ pub unsafe fn Q6_R_lsr_RI(rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(lsr, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_lsracc_RI(rx: i32, rs: i32) -> i32 { @@ -10159,7 +10054,6 @@ pub unsafe fn Q6_R_lsracc_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(lsr, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_lsrand_RI(rx: i32, rs: i32) -> i32 { @@ -10172,7 +10066,6 @@ pub unsafe fn Q6_R_lsrand_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(lsr, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_lsrnac_RI(rx: i32, rs: i32) -> i32 { @@ -10185,7 +10078,6 @@ pub unsafe fn Q6_R_lsrnac_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(lsr, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_lsror_RI(rx: i32, rs: i32) -> i32 { @@ -10198,7 +10090,6 @@ pub unsafe fn Q6_R_lsror_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(lsr, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_lsrxacc_RI(rx: i32, rs: i32) -> i32 { @@ -10211,7 +10102,6 @@ pub unsafe fn Q6_R_lsrxacc_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vlsrh, IU4 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_vlsrh_PI(rss: i64) -> i64 { @@ -10224,7 +10114,6 @@ pub unsafe fn Q6_P_vlsrh_PI(rss: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vlsrw, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_vlsrw_PI(rss: i64) -> i64 { @@ -10402,7 +10291,6 @@ pub unsafe fn Q6_R_parity_PP(rss: i64, rtt: i64) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(setbit, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_setbit_RI(rs: i32) -> i32 { @@ -10492,7 +10380,6 @@ pub unsafe fn Q6_R_vsathub_R(rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(2, 3)] #[cfg_attr(test, assert_instr(tableidxb, IU4 = 0, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_tableidxb_RII(rx: i32, rs: i32) -> i32 { @@ -10506,7 +10393,6 @@ pub unsafe fn Q6_R_tableidxb_RII(rx: i32, rs: i3 /// Instruction Type: S_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(2, 3)] #[cfg_attr(test, assert_instr(tableidxd, IU4 = 0, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_tableidxd_RII(rx: i32, rs: i32) -> i32 { @@ -10520,7 +10406,6 @@ pub unsafe fn Q6_R_tableidxd_RII(rx: i32, rs: i3 /// Instruction Type: S_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(2, 3)] #[cfg_attr(test, assert_instr(tableidxh, IU4 = 0, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_tableidxh_RII(rx: i32, rs: i32) -> i32 { @@ -10534,7 +10419,6 @@ pub unsafe fn Q6_R_tableidxh_RII(rx: i32, rs: i3 /// Instruction Type: S_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(2, 3)] #[cfg_attr(test, assert_instr(tableidxw, IU4 = 0, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_tableidxw_RII(rx: i32, rs: i32) -> i32 { @@ -10548,7 +10432,6 @@ pub unsafe fn Q6_R_tableidxw_RII(rx: i32, rs: i3 /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(togglebit, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_togglebit_RI(rs: i32) -> i32 { @@ -10572,7 +10455,6 @@ pub unsafe fn Q6_R_togglebit_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(tstbit, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_tstbit_RI(rs: i32) -> i32 { @@ -10596,7 +10478,6 @@ pub unsafe fn Q6_p_tstbit_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: S_3op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(valignb, IU3 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_valignb_PPI(rtt: i64, rss: i64) -> i64 { @@ -10785,7 +10666,6 @@ pub unsafe fn Q6_P_vsplath_R(rs: i32) -> i64 { /// Instruction Type: S_3op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vspliceb, IU3 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_vspliceb_PPI(rss: i64, rtt: i64) -> i64 { @@ -10897,7 +10777,6 @@ pub unsafe fn Q6_P_vzxthw_R(rs: i32) -> i64 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(add, IS6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_add_add_RRI(rs: i32, ru: i32) -> i32 { @@ -10910,7 +10789,6 @@ pub unsafe fn Q6_R_add_add_RRI(rs: i32, ru: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0, 2)] #[cfg_attr(test, assert_instr(add, IU8 = 0, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_add_asl_IRI(rx: i32) -> i32 { @@ -10924,7 +10802,6 @@ pub unsafe fn Q6_R_add_asl_IRI(rx: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0, 2)] #[cfg_attr(test, assert_instr(add, IU8 = 0, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_add_lsr_IRI(rx: i32) -> i32 { @@ -10938,7 +10815,6 @@ pub unsafe fn Q6_R_add_lsr_IRI(rx: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0, 2)] #[cfg_attr(test, assert_instr(and, IU8 = 0, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_and_asl_IRI(rx: i32) -> i32 { @@ -10952,7 +10828,6 @@ pub unsafe fn Q6_R_and_asl_IRI(rx: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0, 2)] #[cfg_attr(test, assert_instr(and, IU8 = 0, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_and_lsr_IRI(rx: i32) -> i32 { @@ -10966,7 +10841,6 @@ pub unsafe fn Q6_R_and_lsr_IRI(rx: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(add, IS6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_add_clb_RI(rs: i32) -> i32 { @@ -10979,7 +10853,6 @@ pub unsafe fn Q6_R_add_clb_RI(rs: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(add, IS6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_add_clb_PI(rss: i64) -> i32 { @@ -11003,7 +10876,6 @@ pub unsafe fn Q6_R_normamt_P(rss: i64) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1, 2)] #[cfg_attr(test, assert_instr(extract, IU5 = 0, IU5_2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_extract_RII(rs: i32) -> i32 { @@ -11028,7 +10900,6 @@ pub unsafe fn Q6_R_extract_RP(rs: i32, rtt: i64) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1, 2)] #[cfg_attr(test, assert_instr(extract, IU6 = 0, IU6_2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_extract_PII(rss: i64) -> i64 { @@ -11053,7 +10924,6 @@ pub unsafe fn Q6_P_extract_PP(rss: i64, rtt: i64) -> i64 { /// Instruction Type: S_3op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0)] #[cfg_attr(test, assert_instr(lsl, IS6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_lsl_IR(rt: i32) -> i32 { @@ -11066,7 +10936,6 @@ pub unsafe fn Q6_R_lsl_IR(rt: i32) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_p_not_tstbit_RI(rs: i32) -> i32 { static_assert_uimm_bits!(IU5, 5); @@ -11088,7 +10957,6 @@ pub unsafe fn Q6_p_not_tstbit_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(and, IS10 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_andor_RI(rx: i32, rs: i32) -> i32 { @@ -11101,7 +10969,6 @@ pub unsafe fn Q6_R_andor_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(or, IS10 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_or_and_RRI(ru: i32, rx: i32) -> i32 { @@ -11114,7 +10981,6 @@ pub unsafe fn Q6_R_or_and_RRI(ru: i32, rx: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(or, IS10 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_oror_RI(rx: i32, rs: i32) -> i32 { @@ -11127,7 +10993,6 @@ pub unsafe fn Q6_R_oror_RI(rx: i32, rs: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0, 2)] #[cfg_attr(test, assert_instr(or, IU8 = 0, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_or_asl_IRI(rx: i32) -> i32 { @@ -11141,7 +11006,6 @@ pub unsafe fn Q6_R_or_asl_IRI(rx: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0, 2)] #[cfg_attr(test, assert_instr(or, IU8 = 0, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_or_lsr_IRI(rx: i32) -> i32 { @@ -11166,7 +11030,6 @@ pub unsafe fn Q6_R_parity_RR(rs: i32, rt: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(add, IS6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_add_sub_RIR(rs: i32, ru: i32) -> i32 { @@ -11179,7 +11042,6 @@ pub unsafe fn Q6_R_add_sub_RIR(rs: i32, ru: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0, 2)] #[cfg_attr(test, assert_instr(sub, IU8 = 0, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_sub_asl_IRI(rx: i32) -> i32 { @@ -11193,7 +11055,6 @@ pub unsafe fn Q6_R_sub_asl_IRI(rx: i32) -> i32 { /// Instruction Type: ALU64 /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(0, 2)] #[cfg_attr(test, assert_instr(sub, IU8 = 0, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_sub_lsr_IRI(rx: i32) -> i32 { @@ -11207,7 +11068,6 @@ pub unsafe fn Q6_R_sub_lsr_IRI(rx: i32) -> i32 { /// Instruction Type: S_3op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(vrcrotate, IU2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_vrcrotate_PRI(rss: i64, rt: i32) -> i64 { @@ -11220,7 +11080,6 @@ pub unsafe fn Q6_P_vrcrotate_PRI(rss: i64, rt: i32) -> i64 { /// Instruction Type: S_3op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vrcrotate, IU2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_vrcrotateacc_PRI(rxx: i64, rss: i64, rt: i32) -> i64 { @@ -11299,7 +11158,6 @@ pub unsafe fn Q6_P_vxsubaddw_PP_sat(rss: i64, rtt: i64) -> i64 { /// Instruction Type: S_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vasrhub, IU4 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_vasrhub_PI_rnd_sat(rss: i64) -> i32 { @@ -11312,7 +11170,6 @@ pub unsafe fn Q6_R_vasrhub_PI_rnd_sat(rss: i64) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT23 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vasrhub, IU4 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_vasrhub_PI_sat(rss: i64) -> i32 { @@ -11336,7 +11193,6 @@ pub unsafe fn Q6_R_popcount_P(rss: i64) -> i32 { /// Instruction Type: S_2op /// Execution Slots: SLOT0123 #[inline(always)] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vasrh, IU4 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_vasrh_PI_rnd(rss: i64) -> i64 { @@ -11428,7 +11284,6 @@ pub unsafe fn Q6_l2fetch_AP(rs: i32, rtt: i64) { /// Requires: V60 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(rol, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_rol_PI(rss: i64) -> i64 { @@ -11443,7 +11298,6 @@ pub unsafe fn Q6_P_rol_PI(rss: i64) -> i64 { /// Requires: V60 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(rol, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_rolacc_PI(rxx: i64, rss: i64) -> i64 { @@ -11458,7 +11312,6 @@ pub unsafe fn Q6_P_rolacc_PI(rxx: i64, rss: i64) -> i64 { /// Requires: V60 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(rol, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_roland_PI(rxx: i64, rss: i64) -> i64 { @@ -11473,7 +11326,6 @@ pub unsafe fn Q6_P_roland_PI(rxx: i64, rss: i64) -> i64 { /// Requires: V60 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(rol, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_rolnac_PI(rxx: i64, rss: i64) -> i64 { @@ -11488,7 +11340,6 @@ pub unsafe fn Q6_P_rolnac_PI(rxx: i64, rss: i64) -> i64 { /// Requires: V60 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(rol, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_rolor_PI(rxx: i64, rss: i64) -> i64 { @@ -11503,7 +11354,6 @@ pub unsafe fn Q6_P_rolor_PI(rxx: i64, rss: i64) -> i64 { /// Requires: V60 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(rol, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_rolxacc_PI(rxx: i64, rss: i64) -> i64 { @@ -11518,7 +11368,6 @@ pub unsafe fn Q6_P_rolxacc_PI(rxx: i64, rss: i64) -> i64 { /// Requires: V60 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(rol, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_rol_RI(rs: i32) -> i32 { @@ -11533,7 +11382,6 @@ pub unsafe fn Q6_R_rol_RI(rs: i32) -> i32 { /// Requires: V60 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(rol, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_rolacc_RI(rx: i32, rs: i32) -> i32 { @@ -11548,7 +11396,6 @@ pub unsafe fn Q6_R_rolacc_RI(rx: i32, rs: i32) -> i32 { /// Requires: V60 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(rol, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_roland_RI(rx: i32, rs: i32) -> i32 { @@ -11563,7 +11410,6 @@ pub unsafe fn Q6_R_roland_RI(rx: i32, rs: i32) -> i32 { /// Requires: V60 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(rol, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_rolnac_RI(rx: i32, rs: i32) -> i32 { @@ -11578,7 +11424,6 @@ pub unsafe fn Q6_R_rolnac_RI(rx: i32, rs: i32) -> i32 { /// Requires: V60 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(rol, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_rolor_RI(rx: i32, rs: i32) -> i32 { @@ -11593,7 +11438,6 @@ pub unsafe fn Q6_R_rolor_RI(rx: i32, rs: i32) -> i32 { /// Requires: V60 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v60"))] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(rol, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_rolxacc_RI(rx: i32, rs: i32) -> i32 { @@ -11724,7 +11568,6 @@ pub unsafe fn Q6_R_mpyinac_RR(rx: i32, rs: i32, rt: i32) -> i32 { /// Requires: V66 #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v66"))] -#[rustc_legacy_const_generics(0, 1)] #[cfg_attr(test, assert_instr(mask, IU5 = 0, IU5_2 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_mask_II() -> i32 { @@ -11740,7 +11583,6 @@ pub unsafe fn Q6_R_mask_II() -> i32 { /// Requires: V67, Audio #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(clip, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_R_clip_RI(rs: i32) -> i32 { @@ -11755,7 +11597,6 @@ pub unsafe fn Q6_R_clip_RI(rs: i32) -> i32 { /// Requires: V67, Audio #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(cround, IU6 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_cround_PI(rss: i64) -> i64 { @@ -11783,7 +11624,6 @@ pub unsafe fn Q6_P_cround_PR(rss: i64, rt: i32) -> i64 { /// Requires: V67, Audio #[inline] #[cfg_attr(target_arch = "hexagon", target_feature(enable = "v67,audio"))] -#[rustc_legacy_const_generics(1)] #[cfg_attr(test, assert_instr(vclip, IU5 = 0))] #[unstable(feature = "stdarch_hexagon", issue = "151523")] pub unsafe fn Q6_P_vclip_PI(rss: i64) -> i64 { diff --git a/crates/core_arch/src/mips/msa.rs b/crates/core_arch/src/mips/msa.rs index ebd9558ef5..62818aece1 100644 --- a/crates/core_arch/src/mips/msa.rs +++ b/crates/core_arch/src/mips/msa.rs @@ -1408,7 +1408,6 @@ pub unsafe fn __msa_addv_d(a: v2i64, b: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(addvi.b, IMM5 = 0b10111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_b(a: v16i8) -> v16i8 { static_assert_uimm_bits!(IMM5, 5); @@ -1424,7 +1423,6 @@ pub unsafe fn __msa_addvi_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(addvi.h, IMM5 = 0b10111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_h(a: v8i16) -> v8i16 { static_assert_uimm_bits!(IMM5, 5); @@ -1440,7 +1438,6 @@ pub unsafe fn __msa_addvi_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(addvi.w, IMM5 = 0b10111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_w(a: v4i32) -> v4i32 { static_assert_uimm_bits!(IMM5, 5); @@ -1456,7 +1453,6 @@ pub unsafe fn __msa_addvi_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(addvi.d, IMM5 = 0b10111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_addvi_d(a: v2i64) -> v2i64 { static_assert_uimm_bits!(IMM5, 5); @@ -1487,7 +1483,6 @@ pub unsafe fn __msa_and_v(a: v16u8, b: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(andi.b, IMM8 = 0b10010111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_andi_b(a: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM8, 8); @@ -1939,7 +1934,6 @@ pub unsafe fn __msa_bclr_d(a: v2u64, b: v2u64) -> v2u64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bclri.b, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_b(a: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM3, 3); @@ -1955,7 +1949,6 @@ pub unsafe fn __msa_bclri_b(a: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bclri.h, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_h(a: v8u16) -> v8u16 { static_assert_uimm_bits!(IMM4, 4); @@ -1971,7 +1964,6 @@ pub unsafe fn __msa_bclri_h(a: v8u16) -> v8u16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bclri.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_w(a: v4u32) -> v4u32 { static_assert_uimm_bits!(IMM5, 5); @@ -1987,7 +1979,6 @@ pub unsafe fn __msa_bclri_w(a: v4u32) -> v4u32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bclri.d, IMM6 = 0b111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bclri_d(a: v2u64) -> v2u64 { static_assert_uimm_bits!(IMM6, 6); @@ -2063,7 +2054,6 @@ pub unsafe fn __msa_binsl_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(binsli.b, IMM3 = 0b111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_b(a: v16u8, b: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM3, 3); @@ -2079,7 +2069,6 @@ pub unsafe fn __msa_binsli_b(a: v16u8, b: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(binsli.h, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_h(a: v8u16, b: v8u16) -> v8u16 { static_assert_uimm_bits!(IMM4, 4); @@ -2095,7 +2084,6 @@ pub unsafe fn __msa_binsli_h(a: v8u16, b: v8u16) -> v8u16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(binsli.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_w(a: v4u32, b: v4u32) -> v4u32 { static_assert_uimm_bits!(IMM5, 5); @@ -2111,7 +2099,6 @@ pub unsafe fn __msa_binsli_w(a: v4u32, b: v4u32) -> v4u32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(binsli.d, IMM6 = 0b111111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsli_d(a: v2u64, b: v2u64) -> v2u64 { static_assert_uimm_bits!(IMM6, 6); @@ -2187,7 +2174,6 @@ pub unsafe fn __msa_binsr_d(a: v2u64, b: v2u64, c: v2u64) -> v2u64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(binsri.b, IMM3 = 0b111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_b(a: v16u8, b: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM3, 3); @@ -2203,7 +2189,6 @@ pub unsafe fn __msa_binsri_b(a: v16u8, b: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(binsri.h, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_h(a: v8u16, b: v8u16) -> v8u16 { static_assert_uimm_bits!(IMM4, 4); @@ -2219,7 +2204,6 @@ pub unsafe fn __msa_binsri_h(a: v8u16, b: v8u16) -> v8u16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(binsri.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_w(a: v4u32, b: v4u32) -> v4u32 { static_assert_uimm_bits!(IMM5, 5); @@ -2235,7 +2219,6 @@ pub unsafe fn __msa_binsri_w(a: v4u32, b: v4u32) -> v4u32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(binsri.d, IMM6 = 0b111111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_binsri_d(a: v2u64, b: v2u64) -> v2u64 { static_assert_uimm_bits!(IMM6, 6); @@ -2266,7 +2249,6 @@ pub unsafe fn __msa_bmnz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bmnzi.b, IMM8 = 0b11111111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bmnzi_b(a: v16u8, b: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM8, 8); @@ -2297,7 +2279,6 @@ pub unsafe fn __msa_bmz_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bmzi.b, IMM8 = 0b11111111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bmzi_b(a: v16u8, b: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM8, 8); @@ -2373,7 +2354,6 @@ pub unsafe fn __msa_bneg_d(a: v2u64, b: v2u64) -> v2u64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bnegi.b, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_b(a: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM3, 3); @@ -2389,7 +2369,6 @@ pub unsafe fn __msa_bnegi_b(a: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bnegi.h, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_h(a: v8u16) -> v8u16 { static_assert_uimm_bits!(IMM4, 4); @@ -2405,7 +2384,6 @@ pub unsafe fn __msa_bnegi_h(a: v8u16) -> v8u16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bnegi.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_w(a: v4u32) -> v4u32 { static_assert_uimm_bits!(IMM5, 5); @@ -2421,7 +2399,6 @@ pub unsafe fn __msa_bnegi_w(a: v4u32) -> v4u32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bnegi.d, IMM6 = 0b111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bnegi_d(a: v2u64) -> v2u64 { static_assert_uimm_bits!(IMM6, 6); @@ -2513,7 +2490,6 @@ pub unsafe fn __msa_bsel_v(a: v16u8, b: v16u8, c: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bseli.b, IMM8 = 0b11111111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseli_b(a: v16u8, b: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM8, 8); @@ -2589,7 +2565,6 @@ pub unsafe fn __msa_bset_d(a: v2u64, b: v2u64) -> v2u64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bseti.b, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_b(a: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM3, 3); @@ -2605,7 +2580,6 @@ pub unsafe fn __msa_bseti_b(a: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bseti.h, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_h(a: v8u16) -> v8u16 { static_assert_uimm_bits!(IMM4, 4); @@ -2621,7 +2595,6 @@ pub unsafe fn __msa_bseti_h(a: v8u16) -> v8u16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bseti.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_w(a: v4u32) -> v4u32 { static_assert_uimm_bits!(IMM5, 5); @@ -2637,7 +2610,6 @@ pub unsafe fn __msa_bseti_w(a: v4u32) -> v4u32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(bseti.d, IMM6 = 0b111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_bseti_d(a: v2u64) -> v2u64 { static_assert_uimm_bits!(IMM6, 6); @@ -2770,7 +2742,6 @@ pub unsafe fn __msa_ceq_d(a: v2i64, b: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ceqi.b, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_b(a: v16i8) -> v16i8 { static_assert_simm_bits!(IMM_S5, 5); @@ -2786,7 +2757,6 @@ pub unsafe fn __msa_ceqi_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ceqi.h, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_h(a: v8i16) -> v8i16 { static_assert_simm_bits!(IMM_S5, 5); @@ -2802,7 +2772,6 @@ pub unsafe fn __msa_ceqi_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ceqi.w, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_w(a: v4i32) -> v4i32 { static_assert_simm_bits!(IMM_S5, 5); @@ -2818,7 +2787,6 @@ pub unsafe fn __msa_ceqi_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ceqi.d, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ceqi_d(a: v2i64) -> v2i64 { static_assert_simm_bits!(IMM_S5, 5); @@ -2833,7 +2801,6 @@ pub unsafe fn __msa_ceqi_d(a: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(cfcmsa, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_cfcmsa() -> i32 { static_assert_uimm_bits!(IMM5, 5); @@ -2970,7 +2937,6 @@ pub unsafe fn __msa_cle_u_d(a: v2u64, b: v2u64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clei_s.b, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_b(a: v16i8) -> v16i8 { static_assert_simm_bits!(IMM_S5, 5); @@ -2987,7 +2953,6 @@ pub unsafe fn __msa_clei_s_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clei_s.h, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_h(a: v8i16) -> v8i16 { static_assert_simm_bits!(IMM_S5, 5); @@ -3004,7 +2969,6 @@ pub unsafe fn __msa_clei_s_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clei_s.w, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_w(a: v4i32) -> v4i32 { static_assert_simm_bits!(IMM_S5, 5); @@ -3021,7 +2985,6 @@ pub unsafe fn __msa_clei_s_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clei_s.d, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_s_d(a: v2i64) -> v2i64 { static_assert_simm_bits!(IMM_S5, 5); @@ -3038,7 +3001,6 @@ pub unsafe fn __msa_clei_s_d(a: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clei_u.b, IMM5 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_b(a: v16u8) -> v16i8 { static_assert_uimm_bits!(IMM5, 5); @@ -3055,7 +3017,6 @@ pub unsafe fn __msa_clei_u_b(a: v16u8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clei_u.h, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_h(a: v8u16) -> v8i16 { static_assert_uimm_bits!(IMM5, 5); @@ -3072,7 +3033,6 @@ pub unsafe fn __msa_clei_u_h(a: v8u16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clei_u.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_w(a: v4u32) -> v4i32 { static_assert_uimm_bits!(IMM5, 5); @@ -3089,7 +3049,6 @@ pub unsafe fn __msa_clei_u_w(a: v4u32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clei_u.d, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clei_u_d(a: v2u64) -> v2i64 { static_assert_uimm_bits!(IMM5, 5); @@ -3226,7 +3185,6 @@ pub unsafe fn __msa_clt_u_d(a: v2u64, b: v2u64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clti_s.b, IMM_S5 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_b(a: v16i8) -> v16i8 { static_assert_simm_bits!(IMM_S5, 5); @@ -3243,7 +3201,6 @@ pub unsafe fn __msa_clti_s_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clti_s.h, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_h(a: v8i16) -> v8i16 { static_assert_simm_bits!(IMM_S5, 5); @@ -3260,7 +3217,6 @@ pub unsafe fn __msa_clti_s_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clti_s.w, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_w(a: v4i32) -> v4i32 { static_assert_simm_bits!(IMM_S5, 5); @@ -3277,7 +3233,6 @@ pub unsafe fn __msa_clti_s_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clti_s.d, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_s_d(a: v2i64) -> v2i64 { static_assert_simm_bits!(IMM_S5, 5); @@ -3294,7 +3249,6 @@ pub unsafe fn __msa_clti_s_d(a: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clti_u.b, IMM5 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_b(a: v16u8) -> v16i8 { static_assert_uimm_bits!(IMM5, 5); @@ -3311,7 +3265,6 @@ pub unsafe fn __msa_clti_u_b(a: v16u8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clti_u.h, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_h(a: v8u16) -> v8i16 { static_assert_uimm_bits!(IMM5, 5); @@ -3328,7 +3281,6 @@ pub unsafe fn __msa_clti_u_h(a: v8u16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clti_u.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_w(a: v4u32) -> v4i32 { static_assert_uimm_bits!(IMM5, 5); @@ -3345,7 +3297,6 @@ pub unsafe fn __msa_clti_u_w(a: v4u32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(clti_u.d, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_clti_u_d(a: v2u64) -> v2i64 { static_assert_uimm_bits!(IMM5, 5); @@ -3360,7 +3311,6 @@ pub unsafe fn __msa_clti_u_d(a: v2u64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(copy_s.b, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_b(a: v16i8) -> i32 { static_assert_uimm_bits!(IMM4, 4); @@ -3375,7 +3325,6 @@ pub unsafe fn __msa_copy_s_b(a: v16i8) -> i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(copy_s.h, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_h(a: v8i16) -> i32 { static_assert_uimm_bits!(IMM3, 3); @@ -3390,7 +3339,6 @@ pub unsafe fn __msa_copy_s_h(a: v8i16) -> i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(copy_s.w, IMM2 = 0b11))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_w(a: v4i32) -> i32 { static_assert_uimm_bits!(IMM2, 2); @@ -3405,7 +3353,6 @@ pub unsafe fn __msa_copy_s_w(a: v4i32) -> i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(copy_s.d, IMM1 = 0b1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_s_d(a: v2i64) -> i64 { static_assert_uimm_bits!(IMM1, 1); @@ -3420,7 +3367,6 @@ pub unsafe fn __msa_copy_s_d(a: v2i64) -> i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(copy_u.b, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_b(a: v16i8) -> u32 { static_assert_uimm_bits!(IMM4, 4); @@ -3435,7 +3381,6 @@ pub unsafe fn __msa_copy_u_b(a: v16i8) -> u32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(copy_u.h, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_h(a: v8i16) -> u32 { static_assert_uimm_bits!(IMM3, 3); @@ -3450,7 +3395,6 @@ pub unsafe fn __msa_copy_u_h(a: v8i16) -> u32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(copy_u.w, IMM2 = 0b11))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_w(a: v4i32) -> u32 { static_assert_uimm_bits!(IMM2, 2); @@ -3465,7 +3409,6 @@ pub unsafe fn __msa_copy_u_w(a: v4i32) -> u32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(copy_u.d, IMM1 = 0b1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_copy_u_d(a: v2i64) -> u64 { static_assert_uimm_bits!(IMM1, 1); @@ -3482,7 +3425,6 @@ pub unsafe fn __msa_copy_u_d(a: v2i64) -> u64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ctcmsa, IMM5 = 0b1))] -#[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ctcmsa(a: i32) -> () { static_assert_uimm_bits!(IMM5, 5); @@ -5856,7 +5798,6 @@ pub unsafe fn __msa_ilvr_d(a: v2i64, b: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(insert.b, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_b(a: v16i8, c: i32) -> v16i8 { static_assert_uimm_bits!(IMM4, 4); @@ -5872,7 +5813,6 @@ pub unsafe fn __msa_insert_b(a: v16i8, c: i32) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(insert.h, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_h(a: v8i16, c: i32) -> v8i16 { static_assert_uimm_bits!(IMM3, 3); @@ -5888,7 +5828,6 @@ pub unsafe fn __msa_insert_h(a: v8i16, c: i32) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(insert.w, IMM2 = 0b11))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_w(a: v4i32, c: i32) -> v4i32 { static_assert_uimm_bits!(IMM2, 2); @@ -5904,7 +5843,6 @@ pub unsafe fn __msa_insert_w(a: v4i32, c: i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(insert.d, IMM1 = 0b1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insert_d(a: v2i64, c: i64) -> v2i64 { static_assert_uimm_bits!(IMM1, 1); @@ -5920,7 +5858,6 @@ pub unsafe fn __msa_insert_d(a: v2i64, c: i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(insve.b, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_b(a: v16i8, c: v16i8) -> v16i8 { static_assert_uimm_bits!(IMM4, 4); @@ -5936,7 +5873,6 @@ pub unsafe fn __msa_insve_b(a: v16i8, c: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(insve.h, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_h(a: v8i16, c: v8i16) -> v8i16 { static_assert_uimm_bits!(IMM3, 3); @@ -5952,7 +5888,6 @@ pub unsafe fn __msa_insve_h(a: v8i16, c: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(insve.w, IMM2 = 0b11))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_w(a: v4i32, c: v4i32) -> v4i32 { static_assert_uimm_bits!(IMM2, 2); @@ -5968,7 +5903,6 @@ pub unsafe fn __msa_insve_w(a: v4i32, c: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(insve.d, IMM1 = 0b1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_insve_d(a: v2i64, c: v2i64) -> v2i64 { static_assert_uimm_bits!(IMM1, 1); @@ -5984,7 +5918,6 @@ pub unsafe fn __msa_insve_d(a: v2i64, c: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ld.b, IMM_S10 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_b(mem_addr: *mut u8) -> v16i8 { static_assert_simm_bits!(IMM_S10, 10); @@ -6000,7 +5933,6 @@ pub unsafe fn __msa_ld_b(mem_addr: *mut u8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ld.h, IMM_S11 = -2))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_h(mem_addr: *mut u8) -> v8i16 { static_assert_simm_bits!(IMM_S11, 11); @@ -6017,7 +5949,6 @@ pub unsafe fn __msa_ld_h(mem_addr: *mut u8) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ld.w, IMM_S12 = -4))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_w(mem_addr: *mut u8) -> v4i32 { static_assert_simm_bits!(IMM_S12, 12); @@ -6034,7 +5965,6 @@ pub unsafe fn __msa_ld_w(mem_addr: *mut u8) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ld.d, IMM_S13 = -8))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ld_d(mem_addr: *mut u8) -> v2i64 { static_assert_simm_bits!(IMM_S13, 13); @@ -6051,7 +5981,6 @@ pub unsafe fn __msa_ld_d(mem_addr: *mut u8) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ldi.b, IMM_S10 = -1))] -#[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_b() -> v16i8 { static_assert_simm_bits!(IMM_S10, 10); @@ -6067,7 +5996,6 @@ pub unsafe fn __msa_ldi_b() -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ldi.h, IMM_S10 = -1))] -#[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_h() -> v8i16 { static_assert_simm_bits!(IMM_S10, 10); @@ -6083,7 +6011,6 @@ pub unsafe fn __msa_ldi_h() -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ldi.w, IMM_S10 = -1))] -#[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_w() -> v4i32 { static_assert_simm_bits!(IMM_S10, 10); @@ -6099,7 +6026,6 @@ pub unsafe fn __msa_ldi_w() -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ldi.d, IMM_S10 = -1))] -#[rustc_legacy_const_generics(0)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ldi_d() -> v2i64 { static_assert_simm_bits!(IMM_S10, 10); @@ -6411,7 +6337,6 @@ pub unsafe fn __msa_max_u_d(a: v2u64, b: v2u64) -> v2u64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(maxi_s.b, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_b(a: v16i8) -> v16i8 { static_assert_simm_bits!(IMM_S5, 5); @@ -6427,7 +6352,6 @@ pub unsafe fn __msa_maxi_s_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(maxi_s.h, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_h(a: v8i16) -> v8i16 { static_assert_simm_bits!(IMM_S5, 5); @@ -6443,7 +6367,6 @@ pub unsafe fn __msa_maxi_s_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(maxi_s.w, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_w(a: v4i32) -> v4i32 { static_assert_simm_bits!(IMM_S5, 5); @@ -6459,7 +6382,6 @@ pub unsafe fn __msa_maxi_s_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(maxi_s.d, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_s_d(a: v2i64) -> v2i64 { static_assert_simm_bits!(IMM_S5, 5); @@ -6475,7 +6397,6 @@ pub unsafe fn __msa_maxi_s_d(a: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(maxi_u.b, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_b(a: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM5, 5); @@ -6491,7 +6412,6 @@ pub unsafe fn __msa_maxi_u_b(a: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(maxi_u.h, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_h(a: v8u16) -> v8u16 { static_assert_uimm_bits!(IMM5, 5); @@ -6507,7 +6427,6 @@ pub unsafe fn __msa_maxi_u_h(a: v8u16) -> v8u16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(maxi_u.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_w(a: v4u32) -> v4u32 { static_assert_uimm_bits!(IMM5, 5); @@ -6523,7 +6442,6 @@ pub unsafe fn __msa_maxi_u_w(a: v4u32) -> v4u32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(maxi_u.d, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_maxi_u_d(a: v2u64) -> v2u64 { static_assert_uimm_bits!(IMM5, 5); @@ -6655,7 +6573,6 @@ pub unsafe fn __msa_min_s_d(a: v2i64, b: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(mini_s.b, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_b(a: v16i8) -> v16i8 { static_assert_simm_bits!(IMM_S5, 5); @@ -6671,7 +6588,6 @@ pub unsafe fn __msa_mini_s_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(mini_s.h, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_h(a: v8i16) -> v8i16 { static_assert_simm_bits!(IMM_S5, 5); @@ -6687,7 +6603,6 @@ pub unsafe fn __msa_mini_s_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(mini_s.w, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_w(a: v4i32) -> v4i32 { static_assert_simm_bits!(IMM_S5, 5); @@ -6703,7 +6618,6 @@ pub unsafe fn __msa_mini_s_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(mini_s.d, IMM_S5 = -1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_s_d(a: v2i64) -> v2i64 { static_assert_simm_bits!(IMM_S5, 5); @@ -6775,7 +6689,6 @@ pub unsafe fn __msa_min_u_d(a: v2u64, b: v2u64) -> v2u64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(mini_u.b, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_b(a: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM5, 5); @@ -6791,7 +6704,6 @@ pub unsafe fn __msa_mini_u_b(a: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(mini_u.h, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_h(a: v8u16) -> v8u16 { static_assert_uimm_bits!(IMM5, 5); @@ -6807,7 +6719,6 @@ pub unsafe fn __msa_mini_u_h(a: v8u16) -> v8u16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(mini_u.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_w(a: v4u32) -> v4u32 { static_assert_uimm_bits!(IMM5, 5); @@ -6823,7 +6734,6 @@ pub unsafe fn __msa_mini_u_w(a: v4u32) -> v4u32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(mini_u.d, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_mini_u_d(a: v2u64) -> v2u64 { static_assert_uimm_bits!(IMM5, 5); @@ -7344,7 +7254,6 @@ pub unsafe fn __msa_nor_v(a: v16u8, b: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(nori.b, IMM8 = 0b11111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_nori_b(a: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM8, 8); @@ -7376,7 +7285,6 @@ pub unsafe fn __msa_or_v(a: v16u8, b: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(ori.b, IMM8 = 0b11111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_ori_b(a: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM8, 8); @@ -7556,7 +7464,6 @@ pub unsafe fn __msa_pcnt_d(a: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(sat_s.b, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_b(a: v16i8) -> v16i8 { static_assert_uimm_bits!(IMM3, 3); @@ -7572,7 +7479,6 @@ pub unsafe fn __msa_sat_s_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(sat_s.h, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_h(a: v8i16) -> v8i16 { static_assert_uimm_bits!(IMM4, 4); @@ -7588,7 +7494,6 @@ pub unsafe fn __msa_sat_s_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(sat_s.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_w(a: v4i32) -> v4i32 { static_assert_uimm_bits!(IMM5, 5); @@ -7604,7 +7509,6 @@ pub unsafe fn __msa_sat_s_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(sat_s.d, IMM6 = 0b111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_s_d(a: v2i64) -> v2i64 { static_assert_uimm_bits!(IMM6, 6); @@ -7620,7 +7524,6 @@ pub unsafe fn __msa_sat_s_d(a: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(sat_u.b, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_b(a: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM3, 3); @@ -7636,7 +7539,6 @@ pub unsafe fn __msa_sat_u_b(a: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(sat_u.h, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_h(a: v8u16) -> v8u16 { static_assert_uimm_bits!(IMM4, 4); @@ -7652,7 +7554,6 @@ pub unsafe fn __msa_sat_u_h(a: v8u16) -> v8u16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(sat_u.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_w(a: v4u32) -> v4u32 { static_assert_uimm_bits!(IMM5, 5); @@ -7668,7 +7569,6 @@ pub unsafe fn __msa_sat_u_w(a: v4u32) -> v4u32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(sat_u.d, IMM6 = 0b111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sat_u_d(a: v2u64) -> v2u64 { static_assert_uimm_bits!(IMM6, 6); @@ -7685,7 +7585,6 @@ pub unsafe fn __msa_sat_u_d(a: v2u64) -> v2u64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(shf.b, IMM8 = 0b11111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_shf_b(a: v16i8) -> v16i8 { static_assert_uimm_bits!(IMM8, 8); @@ -7702,7 +7601,6 @@ pub unsafe fn __msa_shf_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(shf.h, IMM8 = 0b11111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_shf_h(a: v8i16) -> v8i16 { static_assert_uimm_bits!(IMM8, 8); @@ -7719,7 +7617,6 @@ pub unsafe fn __msa_shf_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(shf.w, IMM8 = 0b11111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_shf_w(a: v4i32) -> v4i32 { static_assert_uimm_bits!(IMM8, 8); @@ -7824,7 +7721,6 @@ pub unsafe fn __msa_sld_d(a: v2i64, b: v2i64, c: i32) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(sldi.b, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_b(a: v16i8, b: v16i8) -> v16i8 { static_assert_uimm_bits!(IMM4, 4); @@ -7845,7 +7741,6 @@ pub unsafe fn __msa_sldi_b(a: v16i8, b: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(sldi.h, IMM3 = 0b111))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_h(a: v8i16, b: v8i16) -> v8i16 { static_assert_uimm_bits!(IMM3, 3); @@ -7866,7 +7761,6 @@ pub unsafe fn __msa_sldi_h(a: v8i16, b: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(sldi.w, IMM2 = 0b11))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_w(a: v4i32, b: v4i32) -> v4i32 { static_assert_uimm_bits!(IMM2, 2); @@ -7887,7 +7781,6 @@ pub unsafe fn __msa_sldi_w(a: v4i32, b: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(sldi.d, IMM1 = 0b1))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_sldi_d(a: v2i64, b: v2i64) -> v2i64 { static_assert_uimm_bits!(IMM1, 1); @@ -7963,7 +7856,6 @@ pub unsafe fn __msa_sll_d(a: v2i64, b: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(slli.b, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_b(a: v16i8) -> v16i8 { static_assert_uimm_bits!(IMM4, 4); @@ -7979,7 +7871,6 @@ pub unsafe fn __msa_slli_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(slli.h, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_h(a: v8i16) -> v8i16 { static_assert_uimm_bits!(IMM3, 3); @@ -7995,7 +7886,6 @@ pub unsafe fn __msa_slli_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(slli.w, IMM2 = 0b11))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_w(a: v4i32) -> v4i32 { static_assert_uimm_bits!(IMM2, 2); @@ -8011,7 +7901,6 @@ pub unsafe fn __msa_slli_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(slli.d, IMM1 = 0b1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_slli_d(a: v2i64) -> v2i64 { static_assert_uimm_bits!(IMM1, 1); @@ -8086,7 +7975,6 @@ pub unsafe fn __msa_splat_d(a: v2i64, b: i32) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(splati.b, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_b(a: v16i8) -> v16i8 { static_assert_uimm_bits!(IMM4, 4); @@ -8101,7 +7989,6 @@ pub unsafe fn __msa_splati_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(splati.h, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_h(a: v8i16) -> v8i16 { static_assert_uimm_bits!(IMM3, 3); @@ -8116,7 +8003,6 @@ pub unsafe fn __msa_splati_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(splati.w, IMM2 = 0b11))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_w(a: v4i32) -> v4i32 { static_assert_uimm_bits!(IMM2, 2); @@ -8131,7 +8017,6 @@ pub unsafe fn __msa_splati_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(splati.d, IMM1 = 0b1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_splati_d(a: v2i64) -> v2i64 { static_assert_uimm_bits!(IMM1, 1); @@ -8207,7 +8092,6 @@ pub unsafe fn __msa_sra_d(a: v2i64, b: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srai.b, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_b(a: v16i8) -> v16i8 { static_assert_uimm_bits!(IMM3, 3); @@ -8223,7 +8107,6 @@ pub unsafe fn __msa_srai_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srai.h, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_h(a: v8i16) -> v8i16 { static_assert_uimm_bits!(IMM4, 4); @@ -8239,7 +8122,6 @@ pub unsafe fn __msa_srai_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srai.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_w(a: v4i32) -> v4i32 { static_assert_uimm_bits!(IMM5, 5); @@ -8255,7 +8137,6 @@ pub unsafe fn __msa_srai_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srai.d, IMM6 = 0b111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srai_d(a: v2i64) -> v2i64 { static_assert_uimm_bits!(IMM6, 6); @@ -8336,7 +8217,6 @@ pub unsafe fn __msa_srar_d(a: v2i64, b: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srari.b, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_b(a: v16i8) -> v16i8 { static_assert_uimm_bits!(IMM3, 3); @@ -8353,7 +8233,6 @@ pub unsafe fn __msa_srari_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srari.h, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_h(a: v8i16) -> v8i16 { static_assert_uimm_bits!(IMM4, 4); @@ -8370,7 +8249,6 @@ pub unsafe fn __msa_srari_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srari.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_w(a: v4i32) -> v4i32 { static_assert_uimm_bits!(IMM5, 5); @@ -8387,7 +8265,6 @@ pub unsafe fn __msa_srari_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srari.d, IMM6 = 0b111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srari_d(a: v2i64) -> v2i64 { static_assert_uimm_bits!(IMM6, 6); @@ -8463,7 +8340,6 @@ pub unsafe fn __msa_srl_d(a: v2i64, b: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srli.b, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_b(a: v16i8) -> v16i8 { static_assert_uimm_bits!(IMM4, 4); @@ -8479,7 +8355,6 @@ pub unsafe fn __msa_srli_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srli.h, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_h(a: v8i16) -> v8i16 { static_assert_uimm_bits!(IMM3, 3); @@ -8495,7 +8370,6 @@ pub unsafe fn __msa_srli_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srli.w, IMM2 = 0b11))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_w(a: v4i32) -> v4i32 { static_assert_uimm_bits!(IMM2, 2); @@ -8511,7 +8385,6 @@ pub unsafe fn __msa_srli_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srli.d, IMM1 = 0b1))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srli_d(a: v2i64) -> v2i64 { static_assert_uimm_bits!(IMM1, 1); @@ -8592,7 +8465,6 @@ pub unsafe fn __msa_srlr_d(a: v2i64, b: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srlri.b, IMM3 = 0b111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_b(a: v16i8) -> v16i8 { static_assert_uimm_bits!(IMM3, 3); @@ -8609,7 +8481,6 @@ pub unsafe fn __msa_srlri_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srlri.h, IMM4 = 0b1111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_h(a: v8i16) -> v8i16 { static_assert_uimm_bits!(IMM4, 4); @@ -8626,7 +8497,6 @@ pub unsafe fn __msa_srlri_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srlri.w, IMM5 = 0b11111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_w(a: v4i32) -> v4i32 { static_assert_uimm_bits!(IMM5, 5); @@ -8643,7 +8513,6 @@ pub unsafe fn __msa_srlri_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(srlri.d, IMM6 = 0b111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_srlri_d(a: v2i64) -> v2i64 { static_assert_uimm_bits!(IMM6, 6); @@ -8659,7 +8528,6 @@ pub unsafe fn __msa_srlri_d(a: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(st.b, IMM_S10 = -1))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_b(a: v16i8, mem_addr: *mut u8) -> () { static_assert_simm_bits!(IMM_S10, 10); @@ -8675,7 +8543,6 @@ pub unsafe fn __msa_st_b(a: v16i8, mem_addr: *mut u8) -> () #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(st.h, IMM_S11 = -2))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_h(a: v8i16, mem_addr: *mut u8) -> () { static_assert_simm_bits!(IMM_S11, 11); @@ -8692,7 +8559,6 @@ pub unsafe fn __msa_st_h(a: v8i16, mem_addr: *mut u8) -> () #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(st.w, IMM_S12 = -4))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_w(a: v4i32, mem_addr: *mut u8) -> () { static_assert_simm_bits!(IMM_S12, 12); @@ -8709,7 +8575,6 @@ pub unsafe fn __msa_st_w(a: v4i32, mem_addr: *mut u8) -> () #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(st.d, IMM_S13 = -8))] -#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_st_d(a: v2i64, mem_addr: *mut u8) -> () { static_assert_simm_bits!(IMM_S13, 13); @@ -9022,7 +8887,6 @@ pub unsafe fn __msa_subv_d(a: v2i64, b: v2i64) -> v2i64 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(subvi.b, IMM5 = 0b10111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_b(a: v16i8) -> v16i8 { static_assert_uimm_bits!(IMM5, 5); @@ -9038,7 +8902,6 @@ pub unsafe fn __msa_subvi_b(a: v16i8) -> v16i8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(subvi.h, IMM5 = 0b10111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_h(a: v8i16) -> v8i16 { static_assert_uimm_bits!(IMM5, 5); @@ -9054,7 +8917,6 @@ pub unsafe fn __msa_subvi_h(a: v8i16) -> v8i16 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(subvi.w, IMM5 = 0b10111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_w(a: v4i32) -> v4i32 { static_assert_uimm_bits!(IMM5, 5); @@ -9070,7 +8932,6 @@ pub unsafe fn __msa_subvi_w(a: v4i32) -> v4i32 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(subvi.d, IMM5 = 0b10111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_subvi_d(a: v2i64) -> v2i64 { static_assert_uimm_bits!(IMM5, 5); @@ -9174,7 +9035,6 @@ pub unsafe fn __msa_xor_v(a: v16u8, b: v16u8) -> v16u8 { #[inline] #[target_feature(enable = "msa")] #[cfg_attr(test, assert_instr(xori.b, IMM8 = 0b11111111))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_mips", issue = "111198")] pub unsafe fn __msa_xori_b(a: v16u8) -> v16u8 { static_assert_uimm_bits!(IMM8, 8); diff --git a/crates/core_arch/src/powerpc/vsx.rs b/crates/core_arch/src/powerpc/vsx.rs index 5f62aebca9..7f8e8e4fd1 100644 --- a/crates/core_arch/src/powerpc/vsx.rs +++ b/crates/core_arch/src/powerpc/vsx.rs @@ -176,7 +176,6 @@ mod sealed { /// Vector permute. #[inline] #[target_feature(enable = "vsx")] -//#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_powerpc", issue = "111145")] pub unsafe fn vec_xxpermdi(a: T, b: T) -> T where diff --git a/crates/core_arch/src/riscv32/zk.rs b/crates/core_arch/src/riscv32/zk.rs index 34e5fb90a9..ae3d80fa2a 100644 --- a/crates/core_arch/src/riscv32/zk.rs +++ b/crates/core_arch/src/riscv32/zk.rs @@ -51,7 +51,6 @@ unsafe extern "llvm-intrinsic" { /// The `BS` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are /// used. #[target_feature(enable = "zkne")] -#[rustc_legacy_const_generics(2)] // See #1464 // #[cfg_attr(test, assert_instr(aes32esi, BS = 0))] #[inline] @@ -80,7 +79,6 @@ pub fn aes32esi(rs1: u32, rs2: u32) -> u32 { /// The `bs` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are /// used. #[target_feature(enable = "zkne")] -#[rustc_legacy_const_generics(2)] // See #1464 // #[cfg_attr(test, assert_instr(aes32esmi, BS = 0))] #[inline] @@ -108,7 +106,6 @@ pub fn aes32esmi(rs1: u32, rs2: u32) -> u32 { /// The `BS` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are /// used. #[target_feature(enable = "zknd")] -#[rustc_legacy_const_generics(2)] // See #1464 // #[cfg_attr(test, assert_instr(aes32dsi, BS = 0))] #[inline] @@ -137,7 +134,6 @@ pub fn aes32dsi(rs1: u32, rs2: u32) -> u32 { /// The `BS` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are /// used. #[target_feature(enable = "zknd")] -#[rustc_legacy_const_generics(2)] // See #1464 // #[cfg_attr(test, assert_instr(aes32dsmi, BS = 0))] #[inline] diff --git a/crates/core_arch/src/riscv64/zk.rs b/crates/core_arch/src/riscv64/zk.rs index ea5486b391..6903c2ae4f 100644 --- a/crates/core_arch/src/riscv64/zk.rs +++ b/crates/core_arch/src/riscv64/zk.rs @@ -130,7 +130,6 @@ pub fn aes64dsm(rs1: u64, rs2: u64) -> u64 { /// /// The `RNUM` parameter is expected to be a constant value inside the range of `0..=10`. #[target_feature(enable = "zkne_or_zknd")] -#[rustc_legacy_const_generics(1)] #[inline] #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] pub fn aes64ks1i(rs1: u64) -> u64 { diff --git a/crates/core_arch/src/riscv_shared/zk.rs b/crates/core_arch/src/riscv_shared/zk.rs index 6966686731..9902dbabf5 100644 --- a/crates/core_arch/src/riscv_shared/zk.rs +++ b/crates/core_arch/src/riscv_shared/zk.rs @@ -169,7 +169,7 @@ pub fn sha256sum1(rs1: u32) -> u32 { /// C = L(B) = B ⊕ (B ≪ 2) ⊕ (B ≪ 10) ⊕ (B ≪ 18) ⊕ (B ≪ 24) /// ``` /// -/// It can be implemented by `sm4ed` instruction like: +/// It can be implemented by the `sm4ed` instruction like this: /// /// ```no_run /// # #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] @@ -177,16 +177,15 @@ pub fn sha256sum1(rs1: u32) -> u32 { /// # #[cfg(target_arch = "riscv32")] use core::arch::riscv32::sm4ed; /// # #[cfg(target_arch = "riscv64")] use core::arch::riscv64::sm4ed; /// let a = x1 ^ x2 ^ x3 ^ rk; -/// let c0 = sm4ed(x0, a, 0); -/// let c1 = sm4ed(c0, a, 1); // c1 represents c[0..=1], etc. -/// let c2 = sm4ed(c1, a, 2); -/// let c3 = sm4ed(c2, a, 3); +/// let c0 = sm4ed::<0>(x0, a); +/// let c1 = sm4ed::<1>(c0, a); // c1 represents c[0..=1], etc. +/// let c2 = sm4ed::<2>(c1, a); +/// let c3 = sm4ed::<3>(c2, a); /// return c3; // c3 represents c[0..=3] /// # } /// ``` #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] #[target_feature(enable = "zksed")] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(sm4ed, BS = 0))] #[inline] pub fn sm4ed(rs1: u32, rs2: u32) -> u32 { @@ -253,16 +252,15 @@ pub fn sm4ed(rs1: u32, rs2: u32) -> u32 { /// # #[cfg(target_arch = "riscv32")] use core::arch::riscv32::sm4ed; /// # #[cfg(target_arch = "riscv64")] use core::arch::riscv64::sm4ed; /// let a = x1 ^ x2 ^ x3 ^ rk; -/// let c0 = sm4ed(x0, a, 0); -/// let c1 = sm4ed(c0, a, 1); // c1 represents c[0..=1], etc. -/// let c2 = sm4ed(c1, a, 2); -/// let c3 = sm4ed(c2, a, 3); +/// let c0 = sm4ed::<0>(x0, a); +/// let c1 = sm4ed::<1>(c0, a); // c1 represents c[0..=1], etc. +/// let c2 = sm4ed::<2>(c1, a); +/// let c3 = sm4ed::<3>(c2, a); /// return c3; // c3 represents c[0..=3] /// # } /// ``` #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] #[target_feature(enable = "zksed")] -#[rustc_legacy_const_generics(2)] #[cfg_attr(test, assert_instr(sm4ks, BS = 0))] #[inline] pub fn sm4ks(rs1: u32, rs2: u32) -> u32 { diff --git a/crates/stdarch-gen-hexagon/src/scalar.rs b/crates/stdarch-gen-hexagon/src/scalar.rs index 8c7880b58a..a8da2da573 100644 --- a/crates/stdarch-gen-hexagon/src/scalar.rs +++ b/crates/stdarch-gen-hexagon/src/scalar.rs @@ -521,17 +521,6 @@ fn generate_functions(intrinsics: &[ScalarIntrinsic]) -> String { output.push_str("#[inline(always)]\n"); } - // Immediate parameters become const generics but are passed as positional - // arguments at the call site: Q6_R_add_RI(rs, 42) rather than Q6_R_add_RI::<42>(rs). - // This matches the assembly syntax where the immediate is an operand. - if !imm_params.is_empty() { - let indices: Vec = imm_params.iter().map(|(i, _, _)| i.to_string()).collect(); - output.push_str(&format!( - "#[rustc_legacy_const_generics({})]\n", - indices.join(", ") - )); - } - if let Some(instr) = extract_instr_name(&info.asm_syntax) { if imm_params.is_empty() { output.push_str(&format!("#[cfg_attr(test, assert_instr({}))]\n", instr)); diff --git a/crates/stdarch-verify/src/lib.rs b/crates/stdarch-verify/src/lib.rs index 5412ab466a..c681eca1dd 100644 --- a/crates/stdarch-verify/src/lib.rs +++ b/crates/stdarch-verify/src/lib.rs @@ -110,37 +110,21 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { quote! { None } }; - let required_const = find_required_const("rustc_args_required_const", &f.attrs); - let mut legacy_const_generics = - find_required_const("rustc_legacy_const_generics", &f.attrs); - if !required_const.is_empty() && !legacy_const_generics.is_empty() { - panic!( - "Can't have both #[rustc_args_required_const] and \ - #[rustc_legacy_const_generics]" - ); - } + let mut legacy_const_generics = find_legacy_const_generics(&f.attrs); // Newer intrinsics don't have `rustc_legacy_const_generics` - assume they belong at // the end of the argument list - if required_const.is_empty() && legacy_const_generics.is_empty() { + if legacy_const_generics.is_empty() { legacy_const_generics = (arguments.len()..(arguments.len() + const_arguments.len())).collect(); } - // The list of required consts, used to verify the arguments, comes from either the - // `rustc_args_required_const` or the `rustc_legacy_const_generics` attribute. - let required_const = if required_const.is_empty() { - legacy_const_generics.clone() - } else { - required_const - }; - legacy_const_generics.sort(); for (idx, ty) in legacy_const_generics - .into_iter() + .iter() .zip(const_arguments.into_iter()) { - arguments.insert(idx, ty); + arguments.insert(*idx, ty); } // Strip leading underscore from fn name when building a test @@ -162,7 +146,7 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { target_feature: #target_feature, instrs: &[#(#instrs),*], file: stringify!(#path), - required_const: &[#(#required_const),*], + legacy_const_generics: &[#(#legacy_const_generics),*], has_test: #has_test, doc: #doc } @@ -596,7 +580,7 @@ fn find_doc(attrs: &[syn::Attribute]) -> String { .collect() } -fn find_required_const(name: &str, attrs: &[syn::Attribute]) -> Vec { +fn find_legacy_const_generics(attrs: &[syn::Attribute]) -> Vec { attrs .iter() .filter_map(|a| { @@ -607,7 +591,7 @@ fn find_required_const(name: &str, attrs: &[syn::Attribute]) -> Vec { } }) .flat_map(|l| { - if l.path.segments[0].ident == name { + if l.path.segments[0].ident == "rustc_legacy_const_generics" { syn::parse2::(l.tokens.clone()) .unwrap() .args diff --git a/crates/stdarch-verify/tests/arm.rs b/crates/stdarch-verify/tests/arm.rs index 6ba9c17c48..40c132bbe8 100644 --- a/crates/stdarch-verify/tests/arm.rs +++ b/crates/stdarch-verify/tests/arm.rs @@ -11,7 +11,7 @@ struct Function { target_feature: Option<&'static str>, instrs: &'static [&'static str], file: &'static str, - required_const: &'static [usize], + legacy_const_generics: &'static [usize], has_test: bool, doc: &'static str, } @@ -333,7 +333,9 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { // SVE uses generic type parameters to handle void pointers (Type::ConstPtr(Type::GenericParam("T")), Type::ConstPtr(Type::Void)) => (), // SVE const generics use i32 over u64 for usability reasons - (Type::PrimSigned(32), Type::PrimUnsigned(64)) if rust.required_const.contains(&i) => { + (Type::PrimSigned(32), Type::PrimUnsigned(64)) + if rust.legacy_const_generics.contains(&i) => + { () } // svset doesn't have its const argument last as we assumed when building the Function @@ -343,12 +345,12 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { } if *arm_const { nconst += 1; - if !rust.required_const.contains(&i) && !rust.name.starts_with("svset") { + if !rust.legacy_const_generics.contains(&i) && !rust.name.starts_with("svset") { bail!("argument const mismatch"); } } } - if nconst != rust.required_const.len() { + if nconst != rust.legacy_const_generics.len() { bail!("wrong number of const arguments"); } diff --git a/crates/stdarch-verify/tests/mips.rs b/crates/stdarch-verify/tests/mips.rs index ba639c3f92..18502ae5c7 100644 --- a/crates/stdarch-verify/tests/mips.rs +++ b/crates/stdarch-verify/tests/mips.rs @@ -14,7 +14,7 @@ struct Function { target_feature: Option<&'static str>, instrs: &'static [&'static str], file: &'static str, - required_const: &'static [usize], + legacy_const_generics: &'static [usize], has_test: bool, doc: &'static str, } @@ -94,6 +94,26 @@ enum MsaTy { MutVoidPtr, } +impl MsaTy { + fn is_const(&self) -> bool { + matches!( + self, + MsaTy::imm0_1 + | MsaTy::imm0_3 + | MsaTy::imm0_7 + | MsaTy::imm0_15 + | MsaTy::imm0_31 + | MsaTy::imm0_63 + | MsaTy::imm0_255 + | MsaTy::imm_n16_15 + | MsaTy::imm_n512_511 + | MsaTy::imm_n1024_1022 + | MsaTy::imm_n2048_2044 + | MsaTy::imm_n4096_4088 + ) + } +} + impl<'a> From<&'a str> for MsaTy { fn from(s: &'a str) -> MsaTy { match s { @@ -169,6 +189,11 @@ impl std::convert::TryFrom<&'static str> for MsaIntrinsic { arg_tys.push(MsaTy::from(arg)); } + // Some of the functions extracted from mips-msa.h have immediate arguments between non-immediate arguments, + // but Rust const generics are not function arguments and cannot be expressed in a way that matches the header. + // For the sake of verification, rust const generics are treated as "the last arguments to a function". + arg_tys.sort_by(|arg1, arg2| arg1.is_const().cmp(&arg2.is_const())); + // The instruction is the intrinsic name without the __msa_ prefix. let instruction = &id[6..]; let mut instruction = instruction.to_string(); @@ -313,30 +338,15 @@ fn matches(rust: &Function, mips: &MsaIntrinsic) -> Result<(), String> { ), } - let is_const = matches!( - mips_arg, - MsaTy::imm0_1 - | MsaTy::imm0_3 - | MsaTy::imm0_7 - | MsaTy::imm0_15 - | MsaTy::imm0_31 - | MsaTy::imm0_63 - | MsaTy::imm0_255 - | MsaTy::imm_n16_15 - | MsaTy::imm_n512_511 - | MsaTy::imm_n1024_1022 - | MsaTy::imm_n2048_2044 - | MsaTy::imm_n4096_4088 - ); - if is_const { + if mips_arg.is_const() { nconst += 1; - if !rust.required_const.contains(&i) { + if !rust.legacy_const_generics.contains(&i) { bail!("argument const mismatch"); } } } - if nconst != rust.required_const.len() { + if nconst != rust.legacy_const_generics.len() { bail!("wrong number of const arguments"); } diff --git a/crates/stdarch-verify/tests/x86-intel.rs b/crates/stdarch-verify/tests/x86-intel.rs index d2839bb300..fbc999780b 100644 --- a/crates/stdarch-verify/tests/x86-intel.rs +++ b/crates/stdarch-verify/tests/x86-intel.rs @@ -18,7 +18,7 @@ struct Function { target_feature: Option<&'static str>, instrs: &'static [&'static str], file: &'static str, - required_const: &'static [usize], + legacy_const_generics: &'static [usize], has_test: bool, doc: &'static str, } @@ -555,7 +555,7 @@ fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> { bail!("wrong number of arguments on {}", rust.name); } for (i, (a, b)) in intel.parameters.iter().zip(rust.arguments).enumerate() { - let is_const = rust.required_const.contains(&i); + let is_const = rust.legacy_const_generics.contains(&i); equate(b, &a.type_, &a.etype, &intel, is_const)?; } }