diff --git a/boards/stm32h563zi_nucleo/board.h b/boards/stm32h563zi_nucleo/board.h index e2fb1d2..a22959d 100644 --- a/boards/stm32h563zi_nucleo/board.h +++ b/boards/stm32h563zi_nucleo/board.h @@ -196,6 +196,7 @@ extern uint8_t ethRxBufs[BOARD_ETH_RX_DESC_COUNT * BOARD_ETH_RX_BUF_SIZE]; .rxBufs = ethRxBufs, \ .rxDescCount = BOARD_ETH_RX_DESC_COUNT, \ .rxBufSize = BOARD_ETH_RX_BUF_SIZE, \ + .mdioCr = 4, /* HCLK 168 MHz -> MDC = 168/102 ~= 1.6 MHz */ \ .timeout = &g_whalTimeout, \ }, \ } diff --git a/boards/stm32n657a0_nucleo/board.h b/boards/stm32n657a0_nucleo/board.h index e8a0708..7beeb50 100644 --- a/boards/stm32n657a0_nucleo/board.h +++ b/boards/stm32n657a0_nucleo/board.h @@ -315,6 +315,7 @@ extern uint8_t ethRxBufs[BOARD_ETH_RX_DESC_COUNT * BOARD_ETH_RX_BUF_SIZE]; .rxBufs = ethRxBufs, \ .rxDescCount = BOARD_ETH_RX_DESC_COUNT, \ .rxBufSize = BOARD_ETH_RX_BUF_SIZE, \ + .mdioCr = 0, /* HCLK 64 MHz -> MDC = 64/42 ~= 1.5 MHz */ \ .timeout = &g_whalTimeout, \ }, \ } diff --git a/src/eth/stm32h5_eth.c b/src/eth/stm32h5_eth.c index 51e3bb9..4a1bcbb 100644 --- a/src/eth/stm32h5_eth.c +++ b/src/eth/stm32h5_eth.c @@ -152,14 +152,6 @@ static struct { /* Max TX frame size */ #define ETH_MAX_FRAME_SIZE 1536 -/* MDIO clock range select (CR field in MACMDIOAR). The MAC uses this to - * pick the AHB->MDC divider. Values map to AHB freq bands: - * CR=0: 60-100 MHz CR=1: 100-150 MHz - * CR=2: 20-35 MHz CR=3: 35-60 MHz - * CR=4: 150-250MHz CR=5: 250-300 MHz - * HSI default (32 MHz HCLK) -> CR=2. */ -#define ETH_MDIO_CR 2 - #ifdef WHAL_CFG_STM32H5_ETH_DIRECT_API_MAPPING #define whal_Stm32h5_Eth_Init whal_Eth_Init #define whal_Stm32h5_Eth_Deinit whal_Eth_Deinit @@ -447,7 +439,7 @@ whal_Error whal_Stm32h5_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr, whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos, reg) | whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos, - ETH_MDIO_CR) | + cfg->mdioCr) | whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos, ETH_MDIO_GOC_READ) | ETH_MACMDIOAR_MB_Msk); @@ -483,7 +475,7 @@ whal_Error whal_Stm32h5_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr, whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos, reg) | whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos, - ETH_MDIO_CR) | + cfg->mdioCr) | whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos, ETH_MDIO_GOC_WRITE) | ETH_MACMDIOAR_MB_Msk); diff --git a/src/eth/stm32n6_eth.c b/src/eth/stm32n6_eth.c index 836a8f5..3985d2e 100644 --- a/src/eth/stm32n6_eth.c +++ b/src/eth/stm32n6_eth.c @@ -161,9 +161,6 @@ static struct { /* Default burst length */ #define ETH_PBL 32 -/* MDIO clock range for AXI bus */ -#define ETH_MDIO_CR 4 - #ifdef WHAL_CFG_STM32N6_ETH_DIRECT_API_MAPPING #define whal_Stm32n6_Eth_Init whal_Eth_Init #define whal_Stm32n6_Eth_Deinit whal_Eth_Deinit @@ -487,7 +484,7 @@ whal_Error whal_Stm32n6_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr, whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos, reg) | whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos, - ETH_MDIO_CR) | + cfg->mdioCr) | whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos, ETH_MDIO_GOC_READ) | ETH_MACMDIOAR_MB_Msk); @@ -523,7 +520,7 @@ whal_Error whal_Stm32n6_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr, whal_SetBits(ETH_MACMDIOAR_RDA_Msk, ETH_MACMDIOAR_RDA_Pos, reg) | whal_SetBits(ETH_MACMDIOAR_CR_Msk, ETH_MACMDIOAR_CR_Pos, - ETH_MDIO_CR) | + cfg->mdioCr) | whal_SetBits(ETH_MACMDIOAR_GOC_Msk, ETH_MACMDIOAR_GOC_Pos, ETH_MDIO_GOC_WRITE) | ETH_MACMDIOAR_MB_Msk); diff --git a/wolfHAL/eth/stm32h5_eth.h b/wolfHAL/eth/stm32h5_eth.h index 386b3f3..5c8c305 100644 --- a/wolfHAL/eth/stm32h5_eth.h +++ b/wolfHAL/eth/stm32h5_eth.h @@ -61,6 +61,12 @@ typedef struct whal_Stm32h5_Eth_Cfg { uint8_t *rxBufs; /* RX frame buffers (pre-allocated) */ size_t rxDescCount; /* Number of RX descriptors */ size_t rxBufSize; /* Size of each RX buffer in bytes */ + /* MDIO clock range select (CR field in MACMDIOAR). Picks the AHB->MDC + * divider for the board's HCLK; MDC must stay <= 2.5 MHz (IEEE 802.3). + * 0: 60-100 MHz (/42) 1: 100-150 MHz (/62) + * 2: 20-35 MHz (/16) 3: 35-60 MHz (/26) + * 4: 150-250MHz (/102) 5: 250-300 MHz (/124) */ + uint8_t mdioCr; whal_Timeout *timeout; } whal_Stm32h5_Eth_Cfg; diff --git a/wolfHAL/eth/stm32n6_eth.h b/wolfHAL/eth/stm32n6_eth.h index 60ae3f5..339a944 100644 --- a/wolfHAL/eth/stm32n6_eth.h +++ b/wolfHAL/eth/stm32n6_eth.h @@ -67,6 +67,12 @@ typedef struct whal_Stm32n6_Eth_Cfg { uint8_t *rxBufs; /**< RX frame buffers */ size_t rxDescCount; /**< Number of RX descriptors */ size_t rxBufSize; /**< Size of each RX buffer in bytes */ + /* MDIO clock range select (CR field in MACMDIOAR). Picks the AXI->MDC + * divider for the board's HCLK; MDC must stay <= 2.5 MHz (IEEE 802.3). + * 0: 60-100 MHz (/42) 1: 100-150 MHz (/62) + * 2: 20-35 MHz (/16) 3: 35-60 MHz (/26) + * 4: 150-250MHz (/102) 5: 250-300 MHz (/124) */ + uint8_t mdioCr; whal_Timeout *timeout; } whal_Stm32n6_Eth_Cfg;