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regulator: mt6358: fix and drop type prefix in MT6366 regulator node names
The new MT6366 binding does away with the type prefix ("buck_", "ldo_") in the regulator node names. This better matches the PMIC pin names. Remaining underscores in names are also replaced with hyphens. Drop the type prefixes and replace remaining underscores to match the MT6366 binding. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230928085537.3246669-9-wenst@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
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1 file changed

Lines changed: 35 additions & 35 deletions

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‎drivers/regulator/mt6358-regulator.c‎

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -525,68 +525,68 @@ static const struct mt6358_regulator_info mt6358_regulators[] = {
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526526
/* The array is indexed by id(MT6366_ID_XXX) */
527527
static const struct mt6358_regulator_info mt6366_regulators[] = {
528-
MT6366_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
528+
MT6366_BUCK("vdram1", VDRAM1, 500000, 2087500, 12500,
529529
0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f, MT6358_VDRAM1_ANA_CON0, 8),
530-
MT6366_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
530+
MT6366_BUCK("vcore", VCORE, 500000, 1293750, 6250,
531531
0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 1),
532-
MT6366_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
532+
MT6366_BUCK("vpa", VPA, 500000, 3650000, 50000,
533533
0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, MT6358_VPA_ANA_CON0, 3),
534-
MT6366_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
534+
MT6366_BUCK("vproc11", VPROC11, 500000, 1293750, 6250,
535535
0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 1),
536-
MT6366_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
536+
MT6366_BUCK("vproc12", VPROC12, 500000, 1293750, 6250,
537537
0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 2),
538-
MT6366_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
538+
MT6366_BUCK("vgpu", VGPU, 500000, 1293750, 6250,
539539
0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 2),
540-
MT6366_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
540+
MT6366_BUCK("vs2", VS2, 500000, 2087500, 12500,
541541
0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, MT6358_VS2_ANA_CON0, 8),
542-
MT6366_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
542+
MT6366_BUCK("vmodem", VMODEM, 500000, 1293750, 6250,
543543
0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, MT6358_VMODEM_ANA_CON0, 8),
544-
MT6366_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
544+
MT6366_BUCK("vs1", VS1, 1000000, 2587500, 12500,
545545
0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, MT6358_VS1_ANA_CON0, 8),
546-
MT6366_REG_FIXED("ldo_vrf12", VRF12,
546+
MT6366_REG_FIXED("vrf12", VRF12,
547547
MT6358_LDO_VRF12_CON0, 0, 1200000),
548-
MT6366_REG_FIXED("ldo_vio18", VIO18,
548+
MT6366_REG_FIXED("vio18", VIO18,
549549
MT6358_LDO_VIO18_CON0, 0, 1800000),
550-
MT6366_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
551-
MT6366_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
552-
MT6366_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
553-
MT6366_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
554-
MT6366_REG_FIXED("ldo_vaux18", VAUX18,
550+
MT6366_REG_FIXED("vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
551+
MT6366_REG_FIXED("vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
552+
MT6366_REG_FIXED("vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
553+
MT6366_REG_FIXED("vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
554+
MT6366_REG_FIXED("vaux18", VAUX18,
555555
MT6358_LDO_VAUX18_CON0, 0, 1800000),
556-
MT6366_REG_FIXED("ldo_vbif28", VBIF28,
556+
MT6366_REG_FIXED("vbif28", VBIF28,
557557
MT6358_LDO_VBIF28_CON0, 0, 2800000),
558-
MT6366_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
559-
MT6366_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
560-
MT6366_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
561-
MT6366_REG_FIXED("ldo_vaud28", VAUD28,
558+
MT6366_REG_FIXED("vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
559+
MT6366_REG_FIXED("va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
560+
MT6366_REG_FIXED("vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
561+
MT6366_REG_FIXED("vaud28", VAUD28,
562562
MT6358_LDO_VAUD28_CON0, 0, 2800000),
563-
MT6366_LDO("ldo_vdram2", VDRAM2, vdram2,
563+
MT6366_LDO("vdram2", VDRAM2, vdram2,
564564
MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10),
565-
MT6366_LDO("ldo_vsim1", VSIM1, vsim,
565+
MT6366_LDO("vsim1", VSIM1, vsim,
566566
MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
567-
MT6366_LDO("ldo_vibr", VIBR, vibr,
567+
MT6366_LDO("vibr", VIBR, vibr,
568568
MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
569-
MT6366_LDO("ldo_vusb", VUSB, vusb,
569+
MT6366_LDO("vusb", VUSB, vusb,
570570
MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
571-
MT6366_LDO("ldo_vefuse", VEFUSE, vefuse,
571+
MT6366_LDO("vefuse", VEFUSE, vefuse,
572572
MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
573-
MT6366_LDO("ldo_vmch", VMCH, vmch_vemc,
573+
MT6366_LDO("vmch", VMCH, vmch_vemc,
574574
MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
575-
MT6366_LDO("ldo_vemc", VEMC, vmch_vemc,
575+
MT6366_LDO("vemc", VEMC, vmch_vemc,
576576
MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
577-
MT6366_LDO("ldo_vcn33", VCN33, vcn33,
577+
MT6366_LDO("vcn33", VCN33, vcn33,
578578
MT6358_LDO_VCN33_CON0_0, 0, MT6358_VCN33_ANA_CON0, 0x300),
579-
MT6366_LDO("ldo_vmc", VMC, vmc,
579+
MT6366_LDO("vmc", VMC, vmc,
580580
MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
581-
MT6366_LDO("ldo_vsim2", VSIM2, vsim,
581+
MT6366_LDO("vsim2", VSIM2, vsim,
582582
MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
583-
MT6366_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
583+
MT6366_LDO1("vsram-proc11", VSRAM_PROC11, 500000, 1293750, 6250,
584584
MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON0, 0x7f),
585-
MT6366_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
585+
MT6366_LDO1("vsram-others", VSRAM_OTHERS, 500000, 1293750, 6250,
586586
MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON2, 0x7f),
587-
MT6366_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
587+
MT6366_LDO1("vsram-gpu", VSRAM_GPU, 500000, 1293750, 6250,
588588
MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON3, 0x7f),
589-
MT6366_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
589+
MT6366_LDO1("vsram-proc12", VSRAM_PROC12, 500000, 1293750, 6250,
590590
MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON1, 0x7f),
591591
};
592592

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