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akhilpo-qcomRob Clark
akhilpo-qcom
authored and
Rob Clark
committed
drm/msm/a6xx: Rebase GMU register offsets
GMU registers are always at a fixed offset from the GPU base address, a consistency maintained at least within a given architecture generation. In A8x family, the base address of the GMU has changed, but the offsets of the gmu registers remain largely the same. To enable reuse of the gmu code for A8x chipsets, update the gmu register offsets to be relative to the GPU's base address instead of GMU's. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689010/ Message-ID: <20251118-kaana-gpu-support-v4-10-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
1 parent 1ef05ef commit 188db3d

4 files changed

Lines changed: 221 additions & 203 deletions

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‎drivers/gpu/drm/msm/adreno/a6xx_gmu.c‎

Lines changed: 57 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -610,22 +610,19 @@ static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
610610
writel(value, ptr + (offset << 2));
611611
}
612612

613-
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
614-
const char *name);
615-
616613
static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
617614
{
618615
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
619616
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
620617
struct platform_device *pdev = to_platform_device(gmu->dev);
621-
void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
618+
void __iomem *pdcptr = devm_platform_ioremap_resource_byname(pdev, "gmu_pdc");
622619
u32 seqmem0_drv0_reg = REG_A6XX_RSCC_SEQ_MEM_0_DRV0;
623620
void __iomem *seqptr = NULL;
624621
uint32_t pdc_address_offset;
625622
bool pdc_in_aop = false;
626623

627624
if (IS_ERR(pdcptr))
628-
goto err;
625+
return;
629626

630627
if (adreno_is_a650_family(adreno_gpu) ||
631628
adreno_is_a7xx(adreno_gpu))
@@ -638,9 +635,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
638635
pdc_address_offset = 0x30080;
639636

640637
if (!pdc_in_aop) {
641-
seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
638+
seqptr = devm_platform_ioremap_resource_byname(pdev, "gmu_pdc_seq");
642639
if (IS_ERR(seqptr))
643-
goto err;
640+
return;
644641
}
645642

646643
/* Disable SDE clock gating */
@@ -730,12 +727,6 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
730727

731728
/* ensure no writes happen before the uCode is fully written */
732729
wmb();
733-
734-
err:
735-
if (!IS_ERR_OR_NULL(pdcptr))
736-
iounmap(pdcptr);
737-
if (!IS_ERR_OR_NULL(seqptr))
738-
iounmap(seqptr);
739730
}
740731

741732
/*
@@ -1821,27 +1812,6 @@ static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu)
18211812
return 0;
18221813
}
18231814

1824-
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1825-
const char *name)
1826-
{
1827-
void __iomem *ret;
1828-
struct resource *res = platform_get_resource_byname(pdev,
1829-
IORESOURCE_MEM, name);
1830-
1831-
if (!res) {
1832-
DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1833-
return ERR_PTR(-EINVAL);
1834-
}
1835-
1836-
ret = ioremap(res->start, resource_size(res));
1837-
if (!ret) {
1838-
DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1839-
return ERR_PTR(-EINVAL);
1840-
}
1841-
1842-
return ret;
1843-
}
1844-
18451815
static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
18461816
const char *name, irq_handler_t handler)
18471817
{
@@ -1892,7 +1862,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
18921862
{
18931863
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
18941864
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1895-
struct platform_device *pdev = to_platform_device(gmu->dev);
18961865

18971866
mutex_lock(&gmu->lock);
18981867
if (!gmu->initialized) {
@@ -1921,8 +1890,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
19211890
qmp_put(gmu->qmp);
19221891

19231892
iounmap(gmu->mmio);
1924-
if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1925-
iounmap(gmu->rscc);
19261893
gmu->mmio = NULL;
19271894
gmu->rscc = NULL;
19281895

@@ -1949,10 +1916,38 @@ static int cxpd_notifier_cb(struct notifier_block *nb,
19491916
return 0;
19501917
}
19511918

1919+
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1920+
const char *name, resource_size_t *start)
1921+
{
1922+
void __iomem *ret;
1923+
struct resource *res = platform_get_resource_byname(pdev,
1924+
IORESOURCE_MEM, name);
1925+
1926+
if (!res) {
1927+
DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1928+
return ERR_PTR(-EINVAL);
1929+
}
1930+
1931+
ret = ioremap(res->start, resource_size(res));
1932+
if (!ret) {
1933+
DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1934+
return ERR_PTR(-EINVAL);
1935+
}
1936+
1937+
if (start)
1938+
*start = res->start;
1939+
1940+
return ret;
1941+
}
1942+
19521943
int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
19531944
{
19541945
struct platform_device *pdev = of_find_device_by_node(node);
1946+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1947+
struct msm_gpu *gpu = &adreno_gpu->base;
19551948
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1949+
resource_size_t start;
1950+
struct resource *res;
19561951
int ret;
19571952

19581953
if (!pdev)
@@ -1977,12 +1972,21 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
19771972
gmu->nr_clocks = ret;
19781973

19791974
/* Map the GMU registers */
1980-
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1975+
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);
19811976
if (IS_ERR(gmu->mmio)) {
19821977
ret = PTR_ERR(gmu->mmio);
19831978
goto err_mmio;
19841979
}
19851980

1981+
res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0_reg_memory");
1982+
if (!res) {
1983+
ret = -EINVAL;
1984+
goto err_mmio;
1985+
}
1986+
1987+
/* Identify gmu base offset from gpu base address */
1988+
gmu->mmio_offset = (u32)(start - res->start);
1989+
19861990
gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
19871991
if (IS_ERR(gmu->cxpd)) {
19881992
ret = PTR_ERR(gmu->cxpd);
@@ -2024,10 +2028,13 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
20242028

20252029
int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
20262030
{
2031+
struct platform_device *pdev = of_find_device_by_node(node);
20272032
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
2033+
struct msm_gpu *gpu = &adreno_gpu->base;
20282034
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
2029-
struct platform_device *pdev = of_find_device_by_node(node);
20302035
struct device_link *link;
2036+
resource_size_t start;
2037+
struct resource *res;
20312038
int ret;
20322039

20332040
if (!pdev)
@@ -2122,15 +2129,24 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
21222129
goto err_memory;
21232130

21242131
/* Map the GMU registers */
2125-
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
2132+
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);
21262133
if (IS_ERR(gmu->mmio)) {
21272134
ret = PTR_ERR(gmu->mmio);
21282135
goto err_memory;
21292136
}
21302137

2138+
res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, "kgsl_3d0_reg_memory");
2139+
if (!res) {
2140+
ret = -EINVAL;
2141+
goto err_mmio;
2142+
}
2143+
2144+
/* Identify gmu base offset from gpu base address */
2145+
gmu->mmio_offset = (u32)(start - res->start);
2146+
21312147
if (adreno_is_a650_family(adreno_gpu) ||
21322148
adreno_is_a7xx(adreno_gpu)) {
2133-
gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
2149+
gmu->rscc = devm_platform_ioremap_resource_byname(pdev, "rscc");
21342150
if (IS_ERR(gmu->rscc)) {
21352151
ret = -ENODEV;
21362152
goto err_mmio;
@@ -2208,8 +2224,6 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
22082224

22092225
err_mmio:
22102226
iounmap(gmu->mmio);
2211-
if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
2212-
iounmap(gmu->rscc);
22132227
free_irq(gmu->gmu_irq, gmu);
22142228
free_irq(gmu->hfi_irq, gmu);
22152229

‎drivers/gpu/drm/msm/adreno/a6xx_gmu.h‎

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@ struct a6xx_gmu {
6868
struct drm_gpuvm *vm;
6969

7070
void __iomem *mmio;
71+
u32 mmio_offset;
7172
void __iomem *rscc;
7273

7374
int hfi_irq;
@@ -130,20 +131,23 @@ struct a6xx_gmu {
130131
unsigned long status;
131132
};
132133

134+
#define GMU_BYTE_OFFSET(gmu, offset) (((offset) << 2) - (gmu)->mmio_offset)
135+
133136
static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
134137
{
135-
return readl(gmu->mmio + (offset << 2));
138+
/* The 'offset' is based on GPU's start address. Adjust it */
139+
return readl(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset));
136140
}
137141

138142
static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
139143
{
140-
writel(value, gmu->mmio + (offset << 2));
144+
writel(value, gmu->mmio + GMU_BYTE_OFFSET(gmu, offset));
141145
}
142146

143147
static inline void
144148
gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)
145149
{
146-
memcpy_toio(gmu->mmio + (offset << 2), data, size);
150+
memcpy_toio(gmu->mmio + GMU_BYTE_OFFSET(gmu, offset), data, size);
147151
wmb();
148152
}
149153

@@ -160,17 +164,17 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
160164
{
161165
u64 val;
162166

163-
val = (u64) readl(gmu->mmio + (lo << 2));
164-
val |= ((u64) readl(gmu->mmio + (hi << 2)) << 32);
167+
val = gmu_read(gmu, lo);
168+
val |= ((u64) gmu_read(gmu, hi) << 32);
165169

166170
return val;
167171
}
168172

169173
#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
170-
readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
171-
interval, timeout)
174+
readl_poll_timeout((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val, \
175+
cond, interval, timeout)
172176
#define gmu_poll_timeout_atomic(gmu, addr, val, cond, interval, timeout) \
173-
readl_poll_timeout_atomic((gmu)->mmio + ((addr) << 2), val, cond, \
177+
readl_poll_timeout_atomic((gmu)->mmio + (GMU_BYTE_OFFSET(gmu, addr)), val, cond, \
174178
interval, timeout)
175179

176180
static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)

‎drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h‎

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -343,48 +343,48 @@ static const struct a6xx_registers a6xx_gbif_reglist =
343343

344344
static const u32 a6xx_gmu_gx_registers[] = {
345345
/* GMU GX */
346-
0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
347-
0x001e, 0x001e, 0x0020, 0x0023, 0x0026, 0x0026, 0x0028, 0x002b,
348-
0x002e, 0x002e, 0x0030, 0x0033, 0x0036, 0x0036, 0x0038, 0x003b,
349-
0x003e, 0x003e, 0x0040, 0x0043, 0x0046, 0x0046, 0x0080, 0x0084,
350-
0x0100, 0x012b, 0x0140, 0x0140,
346+
0x1a800, 0x1a800, 0x1a810, 0x1a813, 0x1a816, 0x1a816, 0x1a818, 0x1a81b,
347+
0x1a81e, 0x1a81e, 0x1a820, 0x1a823, 0x1a826, 0x1a826, 0x1a828, 0x1a82b,
348+
0x1a82e, 0x1a82e, 0x1a830, 0x1a833, 0x1a836, 0x1a836, 0x1a838, 0x1a83b,
349+
0x1a83e, 0x1a83e, 0x1a840, 0x1a843, 0x1a846, 0x1a846, 0x1a880, 0x1a884,
350+
0x1a900, 0x1a92b, 0x1a940, 0x1a940,
351351
};
352352

353353
static const u32 a6xx_gmu_cx_registers[] = {
354354
/* GMU CX */
355-
0x4c00, 0x4c07, 0x4c10, 0x4c12, 0x4d00, 0x4d00, 0x4d07, 0x4d0a,
356-
0x5000, 0x5004, 0x5007, 0x5008, 0x500b, 0x500c, 0x500f, 0x501c,
357-
0x5024, 0x502a, 0x502d, 0x5030, 0x5040, 0x5053, 0x5087, 0x5089,
358-
0x50a0, 0x50a2, 0x50a4, 0x50af, 0x50c0, 0x50c3, 0x50d0, 0x50d0,
359-
0x50e4, 0x50e4, 0x50e8, 0x50ec, 0x5100, 0x5103, 0x5140, 0x5140,
360-
0x5142, 0x5144, 0x514c, 0x514d, 0x514f, 0x5151, 0x5154, 0x5154,
361-
0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165,
362-
0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc,
363-
0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201,
355+
0x1f400, 0x1f407, 0x1f410, 0x1f412, 0x1f500, 0x1f500, 0x1f507, 0x1f50a,
356+
0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c, 0x1f80f, 0x1f81c,
357+
0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f887, 0x1f889,
358+
0x1f8a0, 0x1f8a2, 0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c3, 0x1f8d0, 0x1f8d0,
359+
0x1f8e4, 0x1f8e4, 0x1f8e8, 0x1f8ec, 0x1f900, 0x1f903, 0x1f940, 0x1f940,
360+
0x1f942, 0x1f944, 0x1f94c, 0x1f94d, 0x1f94f, 0x1f951, 0x1f954, 0x1f954,
361+
0x1f957, 0x1f958, 0x1f95d, 0x1f95d, 0x1f962, 0x1f962, 0x1f964, 0x1f965,
362+
0x1f980, 0x1f986, 0x1f990, 0x1f99e, 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9cc,
363+
0x1f9e0, 0x1f9e2, 0x1f9f0, 0x1f9f0, 0x1fa00, 0x1fa01,
364364
/* GMU AO */
365-
0x9300, 0x9316, 0x9400, 0x9400,
365+
0x23b00, 0x23b16, 0x23c00, 0x23c00,
366366
};
367367

368368
static const u32 a6xx_gmu_gpucc_registers[] = {
369369
/* GPU CC */
370-
0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b,
371-
0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40,
372-
0x9c42, 0x9c49, 0x9c58, 0x9c5a, 0x9d40, 0x9d5e, 0xa000, 0xa002,
373-
0xa400, 0xa402, 0xac00, 0xac02, 0xb000, 0xb002, 0xb400, 0xb402,
374-
0xb800, 0xb802,
370+
0x24000, 0x24012, 0x24040, 0x24052, 0x24400, 0x24404, 0x24407, 0x2440b,
371+
0x24415, 0x2441c, 0x2441e, 0x2442d, 0x2443c, 0x2443d, 0x2443f, 0x24440,
372+
0x24442, 0x24449, 0x24458, 0x2445a, 0x24540, 0x2455e, 0x24800, 0x24802,
373+
0x24c00, 0x24c02, 0x25400, 0x25402, 0x25800, 0x25802, 0x25c00, 0x25c02,
374+
0x26000, 0x26002,
375375
/* GPU CC ACD */
376-
0xbc00, 0xbc16, 0xbc20, 0xbc27,
376+
0x26400, 0x26416, 0x26420, 0x26427,
377377
};
378378

379379
static const u32 a621_gmu_gpucc_registers[] = {
380380
/* GPU CC */
381-
0x9800, 0x980e, 0x9c00, 0x9c0e, 0xb000, 0xb004, 0xb400, 0xb404,
382-
0xb800, 0xb804, 0xbc00, 0xbc05, 0xbc14, 0xbc1d, 0xbc2a, 0xbc30,
383-
0xbc32, 0xbc32, 0xbc41, 0xbc55, 0xbc66, 0xbc68, 0xbc78, 0xbc7a,
384-
0xbc89, 0xbc8a, 0xbc9c, 0xbc9e, 0xbca0, 0xbca3, 0xbcb3, 0xbcb5,
385-
0xbcc5, 0xbcc7, 0xbcd6, 0xbcd8, 0xbce8, 0xbce9, 0xbcf9, 0xbcfc,
386-
0xbd0b, 0xbd0c, 0xbd1c, 0xbd1e, 0xbd40, 0xbd70, 0xbe00, 0xbe16,
387-
0xbe20, 0xbe2d,
381+
0x24000, 0x2400e, 0x24400, 0x2440e, 0x25800, 0x25804, 0x25c00, 0x25c04,
382+
0x26000, 0x26004, 0x26400, 0x26405, 0x26414, 0x2641d, 0x2642a, 0x26430,
383+
0x26432, 0x26432, 0x26441, 0x26455, 0x26466, 0x26468, 0x26478, 0x2647a,
384+
0x26489, 0x2648a, 0x2649c, 0x2649e, 0x264a0, 0x264a3, 0x264b3, 0x264b5,
385+
0x264c5, 0x264c7, 0x264d6, 0x264d8, 0x264e8, 0x264e9, 0x264f9, 0x264fc,
386+
0x2650b, 0x2650c, 0x2651c, 0x2651e, 0x26540, 0x26570, 0x26600, 0x26616,
387+
0x26620, 0x2662d,
388388
};
389389

390390
static const u32 a6xx_gmu_cx_rscc_registers[] = {

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