@@ -1371,7 +1371,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
13711371 struct cxl_endpoint_decoder * cxled )
13721372{
13731373 struct cxl_root_decoder * cxlrd = to_cxl_root_decoder (cxlr -> dev .parent );
1374- int parent_iw , parent_ig , ig , iw , rc , inc = 0 , pos = cxled -> pos ;
1374+ int parent_iw , parent_ig , ig , iw , rc , pos = cxled -> pos ;
13751375 struct cxl_port * parent_port = to_cxl_port (port -> dev .parent );
13761376 struct cxl_region_ref * cxl_rr = cxl_rr_load (port , cxlr );
13771377 struct cxl_memdev * cxlmd = cxled_to_memdev (cxled );
@@ -1563,9 +1563,8 @@ static int cxl_port_setup_targets(struct cxl_port *port,
15631563 cxlsd -> target [cxl_rr -> nr_targets_set ] = ep -> dport ;
15641564 cxlsd -> cxld .target_map [cxl_rr -> nr_targets_set ] = ep -> dport -> port_id ;
15651565 }
1566- inc = 1 ;
1566+ cxl_rr -> nr_targets_set ++ ;
15671567out_target_set :
1568- cxl_rr -> nr_targets_set += inc ;
15691568 dev_dbg (& cxlr -> dev , "%s:%s target[%d] = %s for %s:%s @ %d\n" ,
15701569 dev_name (port -> uport_dev ), dev_name (& port -> dev ),
15711570 cxl_rr -> nr_targets_set - 1 , dev_name (ep -> dport -> dport_dev ),
@@ -2968,16 +2967,6 @@ static bool cxl_is_hpa_in_chunk(u64 hpa, struct cxl_region *cxlr, int pos)
29682967 return false;
29692968}
29702969
2971- static bool has_hpa_to_spa (struct cxl_root_decoder * cxlrd )
2972- {
2973- return cxlrd -> ops && cxlrd -> ops -> hpa_to_spa ;
2974- }
2975-
2976- static bool has_spa_to_hpa (struct cxl_root_decoder * cxlrd )
2977- {
2978- return cxlrd -> ops && cxlrd -> ops -> spa_to_hpa ;
2979- }
2980-
29812970#define CXL_POS_ZERO 0
29822971/**
29832972 * cxl_validate_translation_params
@@ -3151,8 +3140,8 @@ u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
31513140 hpa = hpa_offset + p -> res -> start + p -> cache_size ;
31523141
31533142 /* Root decoder translation overrides typical modulo decode */
3154- if (has_hpa_to_spa ( cxlrd ) )
3155- hpa = cxlrd -> ops -> hpa_to_spa (cxlrd , hpa );
3143+ if (cxlrd -> ops . hpa_to_spa )
3144+ hpa = cxlrd -> ops . hpa_to_spa (cxlrd , hpa );
31563145
31573146 if (!cxl_resource_contains_addr (p -> res , hpa )) {
31583147 dev_dbg (& cxlr -> dev ,
@@ -3161,7 +3150,7 @@ u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
31613150 }
31623151
31633152 /* Simple chunk check, by pos & gran, only applies to modulo decodes */
3164- if (!has_hpa_to_spa ( cxlrd ) && ( !cxl_is_hpa_in_chunk (hpa , cxlr , pos ) ))
3153+ if (!cxlrd -> ops . hpa_to_spa && !cxl_is_hpa_in_chunk (hpa , cxlr , pos ))
31653154 return ULLONG_MAX ;
31663155
31673156 return hpa ;
@@ -3194,8 +3183,8 @@ static int region_offset_to_dpa_result(struct cxl_region *cxlr, u64 offset,
31943183 * If the root decoder has SPA to CXL HPA callback, use it. Otherwise
31953184 * CXL HPA is assumed to equal SPA.
31963185 */
3197- if (has_spa_to_hpa ( cxlrd ) ) {
3198- hpa = cxlrd -> ops -> spa_to_hpa (cxlrd , p -> res -> start + offset );
3186+ if (cxlrd -> ops . spa_to_hpa ) {
3187+ hpa = cxlrd -> ops . spa_to_hpa (cxlrd , p -> res -> start + offset );
31993188 hpa_offset = hpa - p -> res -> start ;
32003189 } else {
32013190 hpa_offset = offset ;
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