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captain5050namhyung
captain5050
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perf vendor events intel: Update sierraforest events from 1.12 to 1.13
The updated events were published in: intel/perfmon@445e38f Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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3 files changed

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‎tools/perf/pmu-events/arch/x86/mapfile.csv‎

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@@ -30,7 +30,7 @@ GenuineIntel-6-CC,v1.02,pantherlake,core
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GenuineIntel-6-A7,v1.04,rocketlake,core
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GenuineIntel-6-2A,v19,sandybridge,core
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GenuineIntel-6-8F,v1.35,sapphirerapids,core
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GenuineIntel-6-AF,v1.12,sierraforest,core
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GenuineIntel-6-AF,v1.13,sierraforest,core
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GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
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GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core
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GenuineIntel-6-55-[01234],v1.37,skylakex,core

‎tools/perf/pmu-events/arch/x86/sierraforest/cache.json‎

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@@ -327,7 +327,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
@@ -338,7 +338,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
@@ -349,7 +349,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
@@ -360,7 +360,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
@@ -371,7 +371,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
@@ -382,7 +382,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
@@ -393,7 +393,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
@@ -404,7 +404,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
@@ -415,7 +415,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
@@ -426,7 +426,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",

‎tools/perf/pmu-events/arch/x86/sierraforest/uncore-cache.json‎

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@@ -9,6 +9,15 @@
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"PublicDescription": "UNC_CHACMS_CLOCKTICKS",
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"Unit": "CHACMS"
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},
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{
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"BriefDescription": "UNC_CHACMS_DISTRESS_ASSERTED",
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"Counter": "0,1,2,3",
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"EventCode": "0x35",
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"EventName": "UNC_CHACMS_DISTRESS_ASSERTED",
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"PerPkg": "1",
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"PortMask": "0x000",
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"Unit": "CHACMS"
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},
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{
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"BriefDescription": "Counts the number of cycles FAST trigger is received from the global FAST distress wire.",
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"Counter": "0,1,2,3",

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