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airliedairlied
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Merge tag 'drm-msm-fixes-2025-08-26' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
Fixes for v6.17-rc4 Core/GPU: - fix comment doc warning in gpuvm - fix build with KMS disabled - fix pgtable setup/teardown race - global fault counter fix - various error path fixes - GPU devcoredump snapshot fixes - handle in-place VM_BIND remaps to solve turnip vm update race - skip re-emitting IBs for unusable VMs - Don't use %pK through printk - moved display snapshot init earlier, fixing a crash DPU: - Fixed crash in virtual plane checking code - Fixed mode comparison in virtual plane checking code DSI: - Adjusted width of resulution-related registers - Fixed locking issue on 14nm PLLs UBWC (per Bjorn's ack) - Added UBWC configuration for several missing platforms (fixing regression) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <rob.clark@oss.qualcomm.com> Link: https://lore.kernel.org/r/CACSVV02+u1VW1dzuz6JWwVEfpgTj6Y-JXMH+vX43KsKTVsW+Yg@mail.gmail.com
2 parents 4b1c24e + 3cf6147 commit 4986258

26 files changed

Lines changed: 301 additions & 197 deletions

‎Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,6 @@ properties:
6060
- const: bus
6161
- const: core
6262
- const: vsync
63-
- const: lut
6463
- const: tbu
6564
- const: tbu_rt
6665
# MSM8996 has additional iommu clock

‎drivers/gpu/drm/drm_gpuvm.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2430,7 +2430,7 @@ static const struct drm_gpuvm_ops lock_ops = {
24302430
* remapped, and locks+prepares (drm_exec_prepare_object()) objects that
24312431
* will be newly mapped.
24322432
*
2433-
* The expected usage is:
2433+
* The expected usage is::
24342434
*
24352435
* .. code-block:: c
24362436
*

‎drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c‎

Lines changed: 33 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
static const unsigned int *gen7_0_0_external_core_regs[] __always_unused;
1212
static const unsigned int *gen7_2_0_external_core_regs[] __always_unused;
1313
static const unsigned int *gen7_9_0_external_core_regs[] __always_unused;
14-
static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] __always_unused;
14+
static const struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] __always_unused;
1515
static const u32 gen7_9_0_cx_debugbus_blocks[] __always_unused;
1616

1717
#include "adreno_gen7_0_0_snapshot.h"
@@ -174,8 +174,15 @@ static int a6xx_crashdumper_run(struct msm_gpu *gpu,
174174
static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset,
175175
u32 *data)
176176
{
177-
u32 reg = A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) |
178-
A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block);
177+
u32 reg;
178+
179+
if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) {
180+
reg = A7XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) |
181+
A7XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block);
182+
} else {
183+
reg = A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(offset) |
184+
A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(block);
185+
}
179186

180187
gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg);
181188
gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg);
@@ -198,11 +205,18 @@ static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset,
198205
readl((ptr) + ((offset) << 2))
199206

200207
/* read a value from the CX debug bus */
201-
static int cx_debugbus_read(void __iomem *cxdbg, u32 block, u32 offset,
208+
static int cx_debugbus_read(struct msm_gpu *gpu, void __iomem *cxdbg, u32 block, u32 offset,
202209
u32 *data)
203210
{
204-
u32 reg = A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) |
205-
A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block);
211+
u32 reg;
212+
213+
if (to_adreno_gpu(gpu)->info->family >= ADRENO_7XX_GEN1) {
214+
reg = A7XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) |
215+
A7XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block);
216+
} else {
217+
reg = A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(offset) |
218+
A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(block);
219+
}
206220

207221
cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A, reg);
208222
cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B, reg);
@@ -315,7 +329,8 @@ static void a6xx_get_debugbus_block(struct msm_gpu *gpu,
315329
ptr += debugbus_read(gpu, block->id, i, ptr);
316330
}
317331

318-
static void a6xx_get_cx_debugbus_block(void __iomem *cxdbg,
332+
static void a6xx_get_cx_debugbus_block(struct msm_gpu *gpu,
333+
void __iomem *cxdbg,
319334
struct a6xx_gpu_state *a6xx_state,
320335
const struct a6xx_debugbus_block *block,
321336
struct a6xx_gpu_state_obj *obj)
@@ -330,7 +345,7 @@ static void a6xx_get_cx_debugbus_block(void __iomem *cxdbg,
330345
obj->handle = block;
331346

332347
for (ptr = obj->data, i = 0; i < block->count; i++)
333-
ptr += cx_debugbus_read(cxdbg, block->id, i, ptr);
348+
ptr += cx_debugbus_read(gpu, cxdbg, block->id, i, ptr);
334349
}
335350

336351
static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu,
@@ -423,8 +438,9 @@ static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu,
423438
a6xx_state, &a7xx_debugbus_blocks[gbif_debugbus_blocks[i]],
424439
&a6xx_state->debugbus[i + debugbus_blocks_count]);
425440
}
426-
}
427441

442+
a6xx_state->nr_debugbus = total_debugbus_blocks;
443+
}
428444
}
429445

430446
static void a6xx_get_debugbus(struct msm_gpu *gpu,
@@ -526,7 +542,8 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
526542
int i;
527543

528544
for (i = 0; i < nr_cx_debugbus_blocks; i++)
529-
a6xx_get_cx_debugbus_block(cxdbg,
545+
a6xx_get_cx_debugbus_block(gpu,
546+
cxdbg,
530547
a6xx_state,
531548
&cx_debugbus_blocks[i],
532549
&a6xx_state->cx_debugbus[i]);
@@ -759,15 +776,15 @@ static void a7xx_get_cluster(struct msm_gpu *gpu,
759776
size_t datasize;
760777
int i, regcount = 0;
761778

762-
/* Some clusters need a selector register to be programmed too */
763-
if (cluster->sel)
764-
in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val);
765-
766779
in += CRASHDUMP_WRITE(in, REG_A7XX_CP_APERTURE_CNTL_CD,
767780
A7XX_CP_APERTURE_CNTL_CD_PIPE(cluster->pipe_id) |
768781
A7XX_CP_APERTURE_CNTL_CD_CLUSTER(cluster->cluster_id) |
769782
A7XX_CP_APERTURE_CNTL_CD_CONTEXT(cluster->context_id));
770783

784+
/* Some clusters need a selector register to be programmed too */
785+
if (cluster->sel)
786+
in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val);
787+
771788
for (i = 0; cluster->regs[i] != UINT_MAX; i += 2) {
772789
int count = RANGE(cluster->regs, i);
773790

@@ -1796,6 +1813,7 @@ static void a7xx_show_shader(struct a6xx_gpu_state_obj *obj,
17961813

17971814
print_name(p, " - type: ", a7xx_statetype_names[block->statetype]);
17981815
print_name(p, " - pipe: ", a7xx_pipe_names[block->pipeid]);
1816+
drm_printf(p, " - location: %d\n", block->location);
17991817

18001818
for (i = 0; i < block->num_sps; i++) {
18011819
drm_printf(p, " - sp: %d\n", i);
@@ -1873,6 +1891,7 @@ static void a7xx_show_dbgahb_cluster(struct a6xx_gpu_state_obj *obj,
18731891
print_name(p, " - pipe: ", a7xx_pipe_names[dbgahb->pipe_id]);
18741892
print_name(p, " - cluster-name: ", a7xx_cluster_names[dbgahb->cluster_id]);
18751893
drm_printf(p, " - context: %d\n", dbgahb->context_id);
1894+
drm_printf(p, " - location: %d\n", dbgahb->location_id);
18761895
a7xx_show_registers_indented(dbgahb->regs, obj->data, p, 4);
18771896
}
18781897
}

‎drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -419,47 +419,47 @@ static const struct a6xx_indexed_registers a6xx_indexed_reglist[] = {
419419
REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
420420
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
421421
REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
422-
{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
422+
{ "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
423423
REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },
424-
{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
424+
{ "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR,
425425
REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},
426426
};
427427

428428
static const struct a6xx_indexed_registers a7xx_indexed_reglist[] = {
429429
{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
430-
REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
430+
REG_A6XX_CP_SQE_STAT_DATA, 0x40, NULL },
431431
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
432432
REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
433-
{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
433+
{ "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
434434
REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },
435-
{ "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR,
436-
REG_A7XX_CP_BV_SQE_STAT_DATA, 0x33, NULL },
437-
{ "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
435+
{ "CP_BV_SQE_STAT", REG_A7XX_CP_BV_SQE_STAT_ADDR,
436+
REG_A7XX_CP_BV_SQE_STAT_DATA, 0x40, NULL },
437+
{ "CP_BV_DRAW_STATE", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
438438
REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x100, NULL },
439-
{ "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
439+
{ "CP_BV_SQE_UCODE_DBG", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
440440
REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x8000, NULL },
441-
{ "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR,
442-
REG_A7XX_CP_SQE_AC_STAT_DATA, 0x33, NULL },
443-
{ "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
441+
{ "CP_SQE_AC_STAT", REG_A7XX_CP_SQE_AC_STAT_ADDR,
442+
REG_A7XX_CP_SQE_AC_STAT_DATA, 0x40, NULL },
443+
{ "CP_LPAC_DRAW_STATE", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
444444
REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x100, NULL },
445-
{ "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
445+
{ "CP_SQE_AC_UCODE_DBG", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
446446
REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x8000, NULL },
447-
{ "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
447+
{ "CP_LPAC_FIFO_DBG", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
448448
REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x40, NULL },
449-
{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
449+
{ "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR,
450450
REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size },
451451
};
452452

453453
static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
454-
"CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
454+
"CP_MEM_POOL_DBG", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
455455
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,
456456
};
457457

458458
static const struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {
459-
{ "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
460-
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL },
461-
{ "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,
462-
REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2100, NULL },
459+
{ "CP_MEM_POOL_DBG", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
460+
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2200, NULL },
461+
{ "CP_BV_MEM_POOL_DBG", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,
462+
REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2200, NULL },
463463
};
464464

465465
#define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }

‎drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h‎

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@ static const u32 gen7_0_0_debugbus_blocks[] = {
8181
A7XX_DBGBUS_USPTP_7,
8282
};
8383

84-
static struct gen7_shader_block gen7_0_0_shader_blocks[] = {
84+
static const struct gen7_shader_block gen7_0_0_shader_blocks[] = {
8585
{A7XX_TP0_TMO_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
8686
{A7XX_TP0_SMO_DATA, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
8787
{A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
@@ -668,12 +668,19 @@ static const u32 gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers[] = {
668668
};
669669
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers), 8));
670670

671-
/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */
672-
static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = {
671+
/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_NONE */
672+
static const u32 gen7_0_0_tpl1_noncontext_pipe_none_registers[] = {
673673
0x0b600, 0x0b600, 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c,
674674
0x0b60f, 0x0b621, 0x0b630, 0x0b633,
675675
UINT_MAX, UINT_MAX,
676676
};
677+
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_none_registers), 8));
678+
679+
/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */
680+
static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = {
681+
0x0b600, 0x0b600,
682+
UINT_MAX, UINT_MAX,
683+
};
677684
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_br_registers), 8));
678685

679686
/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_LPAC */
@@ -695,7 +702,7 @@ static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = {
695702
.val = 0x9,
696703
};
697704

698-
static struct gen7_cluster_registers gen7_0_0_clusters[] = {
705+
static const struct gen7_cluster_registers gen7_0_0_clusters[] = {
699706
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
700707
gen7_0_0_noncontext_pipe_br_registers, },
701708
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
@@ -764,7 +771,7 @@ static struct gen7_cluster_registers gen7_0_0_clusters[] = {
764771
gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
765772
};
766773

767-
static struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = {
774+
static const struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = {
768775
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
769776
gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 },
770777
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
@@ -914,7 +921,7 @@ static const u32 gen7_0_0_dpm_registers[] = {
914921
};
915922
static_assert(IS_ALIGNED(sizeof(gen7_0_0_dpm_registers), 8));
916923

917-
static struct gen7_reg_list gen7_0_0_reg_list[] = {
924+
static const struct gen7_reg_list gen7_0_0_reg_list[] = {
918925
{ gen7_0_0_gpu_registers, NULL },
919926
{ gen7_0_0_cx_misc_registers, NULL },
920927
{ gen7_0_0_dpm_registers, NULL },

‎drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ static const u32 gen7_2_0_debugbus_blocks[] = {
9595
A7XX_DBGBUS_CCHE_2,
9696
};
9797

98-
static struct gen7_shader_block gen7_2_0_shader_blocks[] = {
98+
static const struct gen7_shader_block gen7_2_0_shader_blocks[] = {
9999
{A7XX_TP0_TMO_DATA, 0x200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
100100
{A7XX_TP0_SMO_DATA, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
101101
{A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
@@ -489,7 +489,7 @@ static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = {
489489
.val = 0x9,
490490
};
491491

492-
static struct gen7_cluster_registers gen7_2_0_clusters[] = {
492+
static const struct gen7_cluster_registers gen7_2_0_clusters[] = {
493493
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
494494
gen7_2_0_noncontext_pipe_br_registers, },
495495
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
@@ -558,7 +558,7 @@ static struct gen7_cluster_registers gen7_2_0_clusters[] = {
558558
gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
559559
};
560560

561-
static struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = {
561+
static const struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = {
562562
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
563563
gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 },
564564
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
@@ -573,6 +573,8 @@ static struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = {
573573
gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 },
574574
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
575575
gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 },
576+
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_NONE, 0, A7XX_USPTP,
577+
gen7_0_0_tpl1_noncontext_pipe_none_registers, 0xb600 },
576578
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
577579
gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 },
578580
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
@@ -737,7 +739,7 @@ static const u32 gen7_2_0_dpm_registers[] = {
737739
};
738740
static_assert(IS_ALIGNED(sizeof(gen7_2_0_dpm_registers), 8));
739741

740-
static struct gen7_reg_list gen7_2_0_reg_list[] = {
742+
static const struct gen7_reg_list gen7_2_0_reg_list[] = {
741743
{ gen7_2_0_gpu_registers, NULL },
742744
{ gen7_2_0_cx_misc_registers, NULL },
743745
{ gen7_2_0_dpm_registers, NULL },

‎drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,7 @@ static const u32 gen7_9_0_cx_debugbus_blocks[] = {
117117
A7XX_DBGBUS_GBIF_CX,
118118
};
119119

120-
static struct gen7_shader_block gen7_9_0_shader_blocks[] = {
120+
static const struct gen7_shader_block gen7_9_0_shader_blocks[] = {
121121
{ A7XX_TP0_TMO_DATA, 0x0200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
122122
{ A7XX_TP0_SMO_DATA, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
123123
{ A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
@@ -1116,7 +1116,7 @@ static const struct gen7_sel_reg gen7_9_0_rb_rbp_sel = {
11161116
.val = 0x9,
11171117
};
11181118

1119-
static struct gen7_cluster_registers gen7_9_0_clusters[] = {
1119+
static const struct gen7_cluster_registers gen7_9_0_clusters[] = {
11201120
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
11211121
gen7_9_0_non_context_pipe_br_registers, },
11221122
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
@@ -1185,7 +1185,7 @@ static struct gen7_cluster_registers gen7_9_0_clusters[] = {
11851185
gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers, },
11861186
};
11871187

1188-
static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = {
1188+
static const struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = {
11891189
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
11901190
gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers, 0xae00},
11911191
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
@@ -1294,34 +1294,34 @@ static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = {
12941294
gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000},
12951295
};
12961296

1297-
static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = {
1297+
static const struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = {
12981298
{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
12991299
REG_A6XX_CP_SQE_STAT_DATA, 0x00040},
13001300
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
13011301
REG_A6XX_CP_DRAW_STATE_DATA, 0x00200},
1302-
{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
1302+
{ "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR,
13031303
REG_A6XX_CP_ROQ_DBG_DATA, 0x00800},
1304-
{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
1304+
{ "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
13051305
REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x08000},
1306-
{ "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
1306+
{ "CP_BV_DRAW_STATE", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
13071307
REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x00200},
1308-
{ "CP_BV_ROQ_DBG_ADDR", REG_A7XX_CP_BV_ROQ_DBG_ADDR,
1308+
{ "CP_BV_ROQ_DBG", REG_A7XX_CP_BV_ROQ_DBG_ADDR,
13091309
REG_A7XX_CP_BV_ROQ_DBG_DATA, 0x00800},
1310-
{ "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
1310+
{ "CP_BV_SQE_UCODE_DBG", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
13111311
REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x08000},
1312-
{ "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR,
1312+
{ "CP_BV_SQE_STAT", REG_A7XX_CP_BV_SQE_STAT_ADDR,
13131313
REG_A7XX_CP_BV_SQE_STAT_DATA, 0x00040},
1314-
{ "CP_RESOURCE_TBL", REG_A7XX_CP_RESOURCE_TABLE_DBG_ADDR,
1314+
{ "CP_RESOURCE_TABLE_DBG", REG_A7XX_CP_RESOURCE_TABLE_DBG_ADDR,
13151315
REG_A7XX_CP_RESOURCE_TABLE_DBG_DATA, 0x04100},
1316-
{ "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
1316+
{ "CP_LPAC_DRAW_STATE", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
13171317
REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x00200},
1318-
{ "CP_LPAC_ROQ", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR,
1318+
{ "CP_LPAC_ROQ_DBG", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR,
13191319
REG_A7XX_CP_LPAC_ROQ_DBG_DATA, 0x00200},
1320-
{ "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
1320+
{ "CP_SQE_AC_UCODE_DBG", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
13211321
REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x08000},
1322-
{ "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR,
1322+
{ "CP_SQE_AC_STAT", REG_A7XX_CP_SQE_AC_STAT_ADDR,
13231323
REG_A7XX_CP_SQE_AC_STAT_DATA, 0x00040},
1324-
{ "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
1324+
{ "CP_LPAC_FIFO_DBG", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
13251325
REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x00040},
13261326
{ "CP_AQE_ROQ_0", REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0,
13271327
REG_A7XX_CP_AQE_ROQ_DBG_DATA_0, 0x00100},
@@ -1337,7 +1337,7 @@ static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = {
13371337
REG_A7XX_CP_AQE_STAT_DATA_1, 0x00040},
13381338
};
13391339

1340-
static struct gen7_reg_list gen7_9_0_reg_list[] = {
1340+
static const struct gen7_reg_list gen7_9_0_reg_list[] = {
13411341
{ gen7_9_0_gpu_registers, NULL},
13421342
{ gen7_9_0_cx_misc_registers, NULL},
13431343
{ gen7_9_0_cx_dbgc_registers, NULL},

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