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akhilpo-qcomRob Clark
akhilpo-qcom
authored and
Rob Clark
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drm/msm/adreno: Do CX GBIF config before GMU start
GMU lies on the CX domain and accesses CX GBIF. So do CX GBIF configurations before GMU wakes up. This was not a problem so far, but A840 GPU is very sensitive to this requirement. Also, move these registers to the catalog. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689024/ Message-ID: <20251118-kaana-gpu-support-v4-17-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
1 parent 0700b9f commit 60a4e18

5 files changed

Lines changed: 54 additions & 14 deletions

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‎drivers/gpu/drm/msm/adreno/a6xx_catalog.c‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -672,6 +672,14 @@ static const u32 a690_protect_regs[] = {
672672
};
673673
DECLARE_ADRENO_PROTECT(a690_protect, 48);
674674

675+
static const struct adreno_reglist a640_gbif[] = {
676+
{ REG_A6XX_GBIF_QSB_SIDE0, 0x00071620 },
677+
{ REG_A6XX_GBIF_QSB_SIDE1, 0x00071620 },
678+
{ REG_A6XX_GBIF_QSB_SIDE2, 0x00071620 },
679+
{ REG_A6XX_GBIF_QSB_SIDE3, 0x00071620 },
680+
{ },
681+
};
682+
675683
static const struct adreno_info a6xx_gpus[] = {
676684
{
677685
.chip_ids = ADRENO_CHIP_IDS(0x06010000),
@@ -688,6 +696,7 @@ static const struct adreno_info a6xx_gpus[] = {
688696
.a6xx = &(const struct a6xx_info) {
689697
.hwcg = a612_hwcg,
690698
.protect = &a630_protect,
699+
.gbif_cx = a640_gbif,
691700
.gmu_cgc_mode = 0x00020202,
692701
.prim_fifo_threshold = 0x00080000,
693702
},
@@ -894,6 +903,7 @@ static const struct adreno_info a6xx_gpus[] = {
894903
.a6xx = &(const struct a6xx_info) {
895904
.hwcg = a620_hwcg,
896905
.protect = &a650_protect,
906+
.gbif_cx = a640_gbif,
897907
.gmu_cgc_mode = 0x00020200,
898908
.prim_fifo_threshold = 0x00010000,
899909
},
@@ -916,6 +926,7 @@ static const struct adreno_info a6xx_gpus[] = {
916926
.a6xx = &(const struct a6xx_info) {
917927
.hwcg = a690_hwcg,
918928
.protect = &a650_protect,
929+
.gbif_cx = a640_gbif,
919930
.gmu_cgc_mode = 0x00020200,
920931
.prim_fifo_threshold = 0x00010000,
921932
.bcms = (const struct a6xx_bcm[]) {
@@ -998,6 +1009,7 @@ static const struct adreno_info a6xx_gpus[] = {
9981009
.a6xx = &(const struct a6xx_info) {
9991010
.hwcg = a650_hwcg,
10001011
.protect = &a650_protect,
1012+
.gbif_cx = a640_gbif,
10011013
.gmu_cgc_mode = 0x00020202,
10021014
.prim_fifo_threshold = 0x00300200,
10031015
},
@@ -1024,6 +1036,7 @@ static const struct adreno_info a6xx_gpus[] = {
10241036
.a6xx = &(const struct a6xx_info) {
10251037
.hwcg = a660_hwcg,
10261038
.protect = &a660_protect,
1039+
.gbif_cx = a640_gbif,
10271040
.gmu_cgc_mode = 0x00020000,
10281041
.prim_fifo_threshold = 0x00300200,
10291042
},
@@ -1042,6 +1055,7 @@ static const struct adreno_info a6xx_gpus[] = {
10421055
.a6xx = &(const struct a6xx_info) {
10431056
.hwcg = a690_hwcg,
10441057
.protect = &a660_protect,
1058+
.gbif_cx = a640_gbif,
10451059
.gmu_cgc_mode = 0x00020200,
10461060
.prim_fifo_threshold = 0x00300200,
10471061
},
@@ -1066,6 +1080,7 @@ static const struct adreno_info a6xx_gpus[] = {
10661080
.a6xx = &(const struct a6xx_info) {
10671081
.hwcg = a660_hwcg,
10681082
.protect = &a660_protect,
1083+
.gbif_cx = a640_gbif,
10691084
.gmu_cgc_mode = 0x00020202,
10701085
.prim_fifo_threshold = 0x00200200,
10711086
},
@@ -1112,6 +1127,7 @@ static const struct adreno_info a6xx_gpus[] = {
11121127
.a6xx = &(const struct a6xx_info) {
11131128
.hwcg = a690_hwcg,
11141129
.protect = &a690_protect,
1130+
.gbif_cx = a640_gbif,
11151131
.gmu_cgc_mode = 0x00020200,
11161132
.prim_fifo_threshold = 0x00800200,
11171133
},
@@ -1447,6 +1463,7 @@ static const struct adreno_info a7xx_gpus[] = {
14471463
.a6xx = &(const struct a6xx_info) {
14481464
.hwcg = a702_hwcg,
14491465
.protect = &a650_protect,
1466+
.gbif_cx = a640_gbif,
14501467
.gmu_cgc_mode = 0x00020202,
14511468
.prim_fifo_threshold = 0x0000c000,
14521469
},
@@ -1474,6 +1491,7 @@ static const struct adreno_info a7xx_gpus[] = {
14741491
.hwcg = a730_hwcg,
14751492
.protect = &a730_protect,
14761493
.pwrup_reglist = &a7xx_pwrup_reglist,
1494+
.gbif_cx = a640_gbif,
14771495
.gmu_cgc_mode = 0x00020000,
14781496
},
14791497
.preempt_record_size = 2860 * SZ_1K,
@@ -1495,6 +1513,7 @@ static const struct adreno_info a7xx_gpus[] = {
14951513
.hwcg = a740_hwcg,
14961514
.protect = &a730_protect,
14971515
.pwrup_reglist = &a7xx_pwrup_reglist,
1516+
.gbif_cx = a640_gbif,
14981517
.gmu_chipid = 0x7020100,
14991518
.gmu_cgc_mode = 0x00020202,
15001519
.bcms = (const struct a6xx_bcm[]) {
@@ -1529,6 +1548,7 @@ static const struct adreno_info a7xx_gpus[] = {
15291548
.protect = &a730_protect,
15301549
.pwrup_reglist = &a7xx_pwrup_reglist,
15311550
.ifpc_reglist = &a750_ifpc_reglist,
1551+
.gbif_cx = a640_gbif,
15321552
.gmu_chipid = 0x7050001,
15331553
.gmu_cgc_mode = 0x00020202,
15341554
.bcms = (const struct a6xx_bcm[]) {
@@ -1570,6 +1590,7 @@ static const struct adreno_info a7xx_gpus[] = {
15701590
.protect = &a730_protect,
15711591
.pwrup_reglist = &a7xx_pwrup_reglist,
15721592
.ifpc_reglist = &a750_ifpc_reglist,
1593+
.gbif_cx = a640_gbif,
15731594
.gmu_chipid = 0x7090100,
15741595
.gmu_cgc_mode = 0x00020202,
15751596
.bcms = (const struct a6xx_bcm[]) {
@@ -1602,6 +1623,7 @@ static const struct adreno_info a7xx_gpus[] = {
16021623
.hwcg = a740_hwcg,
16031624
.protect = &a730_protect,
16041625
.pwrup_reglist = &a7xx_pwrup_reglist,
1626+
.gbif_cx = a640_gbif,
16051627
.gmu_chipid = 0x70f0000,
16061628
.gmu_cgc_mode = 0x00020222,
16071629
.bcms = (const struct a6xx_bcm[]) {
@@ -1749,6 +1771,15 @@ static const u32 a840_protect_regs[] = {
17491771
};
17501772
DECLARE_ADRENO_PROTECT(a840_protect, 15);
17511773

1774+
static const struct adreno_reglist a840_gbif[] = {
1775+
{ REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 },
1776+
{ REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 },
1777+
{ REG_A6XX_GBIF_QSB_SIDE2, 0x00071e20 },
1778+
{ REG_A6XX_GBIF_QSB_SIDE3, 0x00071e20 },
1779+
{ REG_A8XX_GBIF_CX_CONFIG, 0x20023000 },
1780+
{ },
1781+
};
1782+
17521783
static const struct adreno_info a8xx_gpus[] = {
17531784
{
17541785
.chip_ids = ADRENO_CHIP_IDS(0x44050a01),
@@ -1766,6 +1797,7 @@ static const struct adreno_info a8xx_gpus[] = {
17661797
.a6xx = &(const struct a6xx_info) {
17671798
.protect = &a840_protect,
17681799
.nonctxt_reglist = a840_nonctxt_regs,
1800+
.gbif_cx = a840_gbif,
17691801
.max_slices = 3,
17701802
.gmu_chipid = 0x8020100,
17711803
.bcms = (const struct a6xx_bcm[]) {

‎drivers/gpu/drm/msm/adreno/a6xx_gmu.c‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -894,7 +894,9 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
894894
{
895895
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
896896
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
897+
struct msm_gpu *gpu = &adreno_gpu->base;
897898
const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx;
899+
const struct adreno_reglist *gbif_cx = a6xx_info->gbif_cx;
898900
u32 fence_range_lower, fence_range_upper;
899901
u32 chipid = 0;
900902
int ret;
@@ -990,6 +992,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
990992
gmu->log.iova | (gmu->log.size / SZ_4K - 1));
991993
}
992994

995+
/* For A7x and newer, do the CX GBIF configurations before GMU wake up */
996+
for (int i = 0; (gbif_cx && gbif_cx[i].offset); i++)
997+
gpu_write(gpu, gbif_cx[i].offset, gbif_cx[i].value);
998+
999+
if (adreno_is_a8xx(adreno_gpu)) {
1000+
gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000);
1001+
gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33);
1002+
}
1003+
9931004
/* Set up the lowest idle level on the GMU */
9941005
a6xx_gmu_power_config(gmu);
9951006

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1279,17 +1279,20 @@ static int hw_init(struct msm_gpu *gpu)
12791279
/* enable hardware clockgating */
12801280
a6xx_set_hwcg(gpu, true);
12811281

1282-
/* VBIF/GBIF start*/
1283-
if (adreno_is_a610_family(adreno_gpu) ||
1284-
adreno_is_a640_family(adreno_gpu) ||
1285-
adreno_is_a650_family(adreno_gpu) ||
1286-
adreno_is_a7xx(adreno_gpu)) {
1282+
/* For gmuwrapper implementations, do the VBIF/GBIF CX configuration here */
1283+
if (adreno_is_a610_family(adreno_gpu)) {
12871284
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
12881285
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
12891286
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
12901287
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
1291-
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL,
1292-
adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3);
1288+
}
1289+
1290+
if (adreno_is_a610_family(adreno_gpu) ||
1291+
adreno_is_a640_family(adreno_gpu) ||
1292+
adreno_is_a650_family(adreno_gpu)) {
1293+
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
1294+
} else if (adreno_is_a7xx(adreno_gpu)) {
1295+
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x2120212);
12931296
} else {
12941297
gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
12951298
}

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ struct a6xx_info {
4646
const struct adreno_protect *protect;
4747
const struct adreno_reglist_list *pwrup_reglist;
4848
const struct adreno_reglist_list *ifpc_reglist;
49+
const struct adreno_reglist *gbif_cx;
4950
const struct adreno_reglist_pipe *nonctxt_reglist;
5051
u32 max_slices;
5152
u32 gmu_chipid;

‎drivers/gpu/drm/msm/adreno/a8xx_gpu.c‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -519,13 +519,6 @@ static int hw_init(struct msm_gpu *gpu)
519519
gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000);
520520
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
521521

522-
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
523-
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
524-
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
525-
gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
526-
gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000);
527-
gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33);
528-
529522
/* Make all blocks contribute to the GPU BUSY perf counter */
530523
gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
531524

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