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vsyrjalavsyrjala
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drm/i915/de: Use intel_de_wait_ms() for the obvious cases
Replace some users of intel_de_wait_custom() with intel_de_wait_ms(). This includes the cases where we pass in the default 2 microsecond fast timeout, which is also what intel_de_wait_ms() uses so there are no functional changes here. Done with cocci (with manual formatting fixes): @@ expression display, reg, mask, value, timeout_ms, out_value; @@ - intel_de_wait_custom(display, reg, mask, value, 2, timeout_ms, out_value) + intel_de_wait_ms(display, reg, mask, value, timeout_ms, out_value) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251110172756.2132-7-ville.syrjala@linux.intel.com Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com>
1 parent 45554c1 commit 8da977a

5 files changed

Lines changed: 30 additions & 34 deletions

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‎drivers/gpu/drm/i915/display/intel_cx0_phy.c‎

Lines changed: 7 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -164,11 +164,10 @@ int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
164164
enum port port = encoder->port;
165165
enum phy phy = intel_encoder_to_phy(encoder);
166166

167-
if (intel_de_wait_custom(display,
168-
XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
169-
XELPDP_PORT_P2M_RESPONSE_READY,
170-
XELPDP_PORT_P2M_RESPONSE_READY,
171-
2, XELPDP_MSGBUS_TIMEOUT_MS, val)) {
167+
if (intel_de_wait_ms(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
168+
XELPDP_PORT_P2M_RESPONSE_READY,
169+
XELPDP_PORT_P2M_RESPONSE_READY,
170+
XELPDP_MSGBUS_TIMEOUT_MS, val)) {
172171
drm_dbg_kms(display->drm,
173172
"PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
174173
phy_name(phy), *val);
@@ -2827,9 +2826,9 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
28272826
intel_cx0_get_powerdown_update(lane_mask));
28282827

28292828
/* Update Timeout Value */
2830-
if (intel_de_wait_custom(display, buf_ctl2_reg,
2831-
intel_cx0_get_powerdown_update(lane_mask), 0,
2832-
2, XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
2829+
if (intel_de_wait_ms(display, buf_ctl2_reg,
2830+
intel_cx0_get_powerdown_update(lane_mask), 0,
2831+
XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
28332832
drm_warn(display->drm,
28342833
"PHY %c failed to bring out of lane reset\n",
28352834
phy_name(phy));

‎drivers/gpu/drm/i915/display/intel_dp_aux.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -62,9 +62,9 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
6262
u32 status;
6363
int ret;
6464

65-
ret = intel_de_wait_custom(display, ch_ctl, DP_AUX_CH_CTL_SEND_BUSY,
66-
0,
67-
2, timeout_ms, &status);
65+
ret = intel_de_wait_ms(display, ch_ctl,
66+
DP_AUX_CH_CTL_SEND_BUSY, 0,
67+
timeout_ms, &status);
6868

6969
if (ret == -ETIMEDOUT)
7070
drm_err(display->drm,

‎drivers/gpu/drm/i915/display/intel_hdcp.c‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -410,9 +410,8 @@ static int intel_hdcp_load_keys(struct intel_display *display)
410410
}
411411

412412
/* Wait for the keys to load (500us) */
413-
ret = intel_de_wait_custom(display, HDCP_KEY_STATUS,
414-
HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
415-
2, 1, &val);
413+
ret = intel_de_wait_ms(display, HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE,
414+
HDCP_KEY_LOAD_DONE, 1, &val);
416415
if (ret)
417416
return ret;
418417
else if (!(val & HDCP_KEY_LOAD_STATUS))

‎drivers/gpu/drm/i915/display/intel_lt_phy.c‎

Lines changed: 15 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1201,10 +1201,9 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
12011201
XELPDP_LANE_PCLK_PLL_REQUEST(0),
12021202
XELPDP_LANE_PCLK_PLL_REQUEST(0));
12031203

1204-
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
1205-
XELPDP_LANE_PCLK_PLL_ACK(0),
1206-
XELPDP_LANE_PCLK_PLL_ACK(0),
1207-
2, XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
1204+
if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
1205+
XELPDP_LANE_PCLK_PLL_ACK(0), XELPDP_LANE_PCLK_PLL_ACK(0),
1206+
XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
12081207
drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack not done\n",
12091208
phy_name(phy));
12101209

@@ -1215,15 +1214,15 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
12151214
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
12161215
lane_pipe_reset | lane_phy_pulse_status, 0);
12171216

1218-
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
1219-
lane_phy_current_status, 0,
1220-
2, XE3PLPD_RESET_END_LATENCY_MS, NULL))
1217+
if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
1218+
lane_phy_current_status, 0,
1219+
XE3PLPD_RESET_END_LATENCY_MS, NULL))
12211220
drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n",
12221221
phy_name(phy));
12231222

1224-
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
1225-
lane_phy_pulse_status, lane_phy_pulse_status,
1226-
2, XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
1223+
if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
1224+
lane_phy_pulse_status, lane_phy_pulse_status,
1225+
XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
12271226
drm_warn(display->drm, "PHY %c PLL rate not changed\n",
12281227
phy_name(phy));
12291228

@@ -2002,10 +2001,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
20022001
XELPDP_LANE_PCLK_PLL_REQUEST(0));
20032002

20042003
/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
2005-
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
2006-
XELPDP_LANE_PCLK_PLL_ACK(0),
2007-
XELPDP_LANE_PCLK_PLL_ACK(0),
2008-
2, XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
2004+
if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
2005+
XELPDP_LANE_PCLK_PLL_ACK(0), XELPDP_LANE_PCLK_PLL_ACK(0),
2006+
XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
20092007
drm_warn(display->drm, "PHY %c PLL MacCLK ack assertion timeout\n",
20102008
phy_name(phy));
20112009

@@ -2031,9 +2029,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
20312029
rate_update, MB_WRITE_COMMITTED);
20322030

20332031
/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
2034-
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
2035-
lane_phy_pulse_status, lane_phy_pulse_status,
2036-
2, XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
2032+
if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
2033+
lane_phy_pulse_status, lane_phy_pulse_status,
2034+
XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
20372035
drm_warn(display->drm, "PHY %c PLL rate not changed\n",
20382036
phy_name(phy));
20392037

‎drivers/gpu/drm/i915/display/intel_pmdemand.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -462,9 +462,9 @@ static void intel_pmdemand_poll(struct intel_display *display)
462462
u32 status;
463463
int ret;
464464

465-
ret = intel_de_wait_custom(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
466-
XELPDP_PMDEMAND_REQ_ENABLE, 0,
467-
2, timeout_ms, &status);
465+
ret = intel_de_wait_ms(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
466+
XELPDP_PMDEMAND_REQ_ENABLE, 0,
467+
timeout_ms, &status);
468468

469469
if (ret == -ETIMEDOUT)
470470
drm_err(display->drm,

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