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9 | 9 | #include <linux/gpio/consumer.h> |
10 | 10 | #include <linux/module.h> |
11 | 11 | #include <linux/delay.h> |
| 12 | +#include <linux/platform_data/edma.h> |
12 | 13 | #include <linux/platform_device.h> |
13 | 14 | #include <linux/err.h> |
14 | 15 | #include <linux/clk.h> |
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19 | 20 | #include <linux/spi/spi_bitbang.h> |
20 | 21 | #include <linux/slab.h> |
21 | 22 |
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22 | | -#include <linux/platform_data/spi-davinci.h> |
23 | | - |
24 | 23 | #define CS_DEFAULT 0xFF |
25 | 24 |
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26 | 25 | #define SPIFMT_PHASE_MASK BIT(16) |
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98 | 97 | #define SPIDEF 0x4c |
99 | 98 | #define SPIFMT0 0x50 |
100 | 99 |
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| 100 | +#define SPI_IO_TYPE_POLL 1 |
| 101 | +#define SPI_IO_TYPE_DMA 2 |
| 102 | + |
101 | 103 | #define DMA_MIN_BYTES 16 |
102 | 104 |
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| 105 | +enum { |
| 106 | + SPI_VERSION_1, /* For DM355/DM365/DM6467 */ |
| 107 | + SPI_VERSION_2, /* For DA8xx */ |
| 108 | +}; |
| 109 | + |
| 110 | +/** |
| 111 | + * struct davinci_spi_platform_data - Platform data for SPI master device on DaVinci |
| 112 | + * |
| 113 | + * @version: version of the SPI IP. Different DaVinci devices have slightly |
| 114 | + * varying versions of the same IP. |
| 115 | + * @num_chipselect: number of chipselects supported by this SPI master |
| 116 | + * @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt |
| 117 | + * controller withn the SoC. Possible values are 0 and 1. |
| 118 | + * @prescaler_limit: max clock prescaler value |
| 119 | + * @cshold_bug: set this to true if the SPI controller on your chip requires |
| 120 | + * a write to CSHOLD bit in between transfers (like in DM355). |
| 121 | + * @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any |
| 122 | + * device on the bus. |
| 123 | + */ |
| 124 | +struct davinci_spi_platform_data { |
| 125 | + u8 version; |
| 126 | + u8 num_chipselect; |
| 127 | + u8 intr_line; |
| 128 | + u8 prescaler_limit; |
| 129 | + bool cshold_bug; |
| 130 | + enum dma_event_q dma_event_q; |
| 131 | +}; |
| 132 | + |
| 133 | +/** |
| 134 | + * struct davinci_spi_config - Per-chip-select configuration for SPI slave devices |
| 135 | + * |
| 136 | + * @wdelay: amount of delay between transmissions. Measured in number of |
| 137 | + * SPI module clocks. |
| 138 | + * @odd_parity: polarity of parity flag at the end of transmit data stream. |
| 139 | + * 0 - odd parity, 1 - even parity. |
| 140 | + * @parity_enable: enable transmission of parity at end of each transmit |
| 141 | + * data stream. |
| 142 | + * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. |
| 143 | + * @timer_disable: disable chip-select timers (setup and hold) |
| 144 | + * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. |
| 145 | + * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. |
| 146 | + * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured |
| 147 | + * in number of SPI clocks. |
| 148 | + * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in |
| 149 | + * number of SPI clocks. |
| 150 | + */ |
| 151 | +struct davinci_spi_config { |
| 152 | + u8 wdelay; |
| 153 | + u8 odd_parity; |
| 154 | + u8 parity_enable; |
| 155 | + u8 io_type; |
| 156 | + u8 timer_disable; |
| 157 | + u8 c2tdelay; |
| 158 | + u8 t2cdelay; |
| 159 | + u8 t2edelay; |
| 160 | + u8 c2edelay; |
| 161 | +}; |
| 162 | + |
103 | 163 | /* SPI Controller driver's private data. */ |
104 | 164 | struct davinci_spi { |
105 | 165 | struct spi_bitbang bitbang; |
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