2121
2222static void sun8i_vi_layer_disable (struct sun8i_layer * layer )
2323{
24- struct sun8i_mixer * mixer = layer -> mixer ;
25- u32 ch_base = sun8i_channel_base (mixer , layer -> channel );
24+ u32 ch_base = sun8i_channel_base (layer );
2625
27- regmap_write (mixer -> engine . regs ,
26+ regmap_write (layer -> regs ,
2827 SUN8I_MIXER_CHAN_VI_LAYER_ATTR (ch_base , layer -> overlay ), 0 );
2928}
3029
3130static void sun8i_vi_layer_update_attributes (struct sun8i_layer * layer ,
3231 struct drm_plane * plane )
3332{
3433 struct drm_plane_state * state = plane -> state ;
35- struct sun8i_mixer * mixer = layer -> mixer ;
3634 const struct drm_format_info * fmt ;
3735 u32 val , ch_base , hw_fmt ;
3836
39- ch_base = sun8i_channel_base (mixer , layer -> channel );
37+ ch_base = sun8i_channel_base (layer );
4038 fmt = state -> fb -> format ;
4139 sun8i_mixer_drm_format_to_hw (fmt -> format , & hw_fmt );
4240
4341 val = hw_fmt << SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET ;
4442 if (!fmt -> is_yuv )
4543 val |= SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE ;
4644 val |= SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN ;
47- if (mixer -> cfg -> de_type >= SUN8I_MIXER_DE3 ) {
45+ if (layer -> cfg -> de_type >= SUN8I_MIXER_DE3 ) {
4846 val |= SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA (state -> alpha >> 8 );
4947 val |= (state -> alpha == DRM_BLEND_ALPHA_OPAQUE ) ?
5048 SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_PIXEL :
@@ -54,7 +52,7 @@ static void sun8i_vi_layer_update_attributes(struct sun8i_layer *layer,
5452 regmap_write (layer -> regs ,
5553 SUN8I_MIXER_CHAN_VI_LAYER_ATTR (ch_base , layer -> overlay ), val );
5654
57- if (mixer -> cfg -> lay_cfg . de2_fcc_alpha ) {
55+ if (layer -> cfg -> de2_fcc_alpha ) {
5856 regmap_write (layer -> regs ,
5957 SUN8I_MIXER_FCC_GLOBAL_ALPHA_REG ,
6058 SUN8I_MIXER_FCC_GLOBAL_ALPHA (state -> alpha >> 8 ));
@@ -78,7 +76,7 @@ static void sun8i_vi_layer_update_coord(struct sun8i_layer *layer,
7876 DRM_DEBUG_DRIVER ("Updating VI channel %d overlay %d\n" ,
7977 layer -> channel , layer -> overlay );
8078
81- ch_base = sun8i_channel_base (mixer , layer -> channel );
79+ ch_base = sun8i_channel_base (layer );
8280
8381 src_w = drm_rect_width (& state -> src ) >> 16 ;
8482 src_h = drm_rect_height (& state -> src ) >> 16 ;
@@ -153,7 +151,7 @@ static void sun8i_vi_layer_update_coord(struct sun8i_layer *layer,
153151 }
154152
155153 /* it seems that every RGB scaler has buffer for 2048 pixels */
156- scanline = subsampled ? mixer -> cfg -> lay_cfg . scanline_yuv : 2048 ;
154+ scanline = subsampled ? layer -> cfg -> scanline_yuv : 2048 ;
157155
158156 if (src_w > scanline ) {
159157 DRM_DEBUG_DRIVER ("Using horizontal coarse scaling\n" );
@@ -195,7 +193,6 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_layer *layer,
195193 struct drm_plane * plane )
196194{
197195 struct drm_plane_state * state = plane -> state ;
198- struct sun8i_mixer * mixer = layer -> mixer ;
199196 struct drm_framebuffer * fb = state -> fb ;
200197 const struct drm_format_info * format = fb -> format ;
201198 struct drm_gem_dma_object * gem ;
@@ -204,7 +201,7 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_layer *layer,
204201 u32 ch_base ;
205202 int i ;
206203
207- ch_base = sun8i_channel_base (mixer , layer -> channel );
204+ ch_base = sun8i_channel_base (layer );
208205
209206 /* Adjust x and y to be dividable by subsampling factor */
210207 src_x = (state -> src .x1 >> 16 ) & ~(format -> hsub - 1 );
@@ -278,7 +275,7 @@ static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
278275 min_scale = DRM_PLANE_NO_SCALING ;
279276 max_scale = DRM_PLANE_NO_SCALING ;
280277
281- if (layer -> mixer -> cfg -> lay_cfg . scaler_mask & BIT (layer -> channel )) {
278+ if (layer -> cfg -> scaler_mask & BIT (layer -> channel )) {
282279 min_scale = SUN8I_VI_SCALER_SCALE_MIN ;
283280 max_scale = SUN8I_VI_SCALER_SCALE_MAX ;
284281 }
@@ -414,7 +411,8 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
414411 enum drm_plane_type type ,
415412 struct regmap * regs ,
416413 int index , int phy_index ,
417- int plane_cnt )
414+ int plane_cnt ,
415+ const struct sun8i_layer_cfg * cfg )
418416{
419417 u32 supported_encodings , supported_ranges ;
420418 unsigned int format_count ;
@@ -432,8 +430,9 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
432430 layer -> channel = phy_index ;
433431 layer -> overlay = 0 ;
434432 layer -> regs = regs ;
433+ layer -> cfg = cfg ;
435434
436- if (mixer -> cfg -> de_type >= SUN8I_MIXER_DE3 ) {
435+ if (layer -> cfg -> de_type >= SUN8I_MIXER_DE3 ) {
437436 formats = sun8i_vi_layer_de3_formats ;
438437 format_count = ARRAY_SIZE (sun8i_vi_layer_de3_formats );
439438 } else {
@@ -452,7 +451,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
452451 return ERR_PTR (ret );
453452 }
454453
455- if (mixer -> cfg -> lay_cfg . de2_fcc_alpha || mixer -> cfg -> de_type >= SUN8I_MIXER_DE3 ) {
454+ if (layer -> cfg -> de2_fcc_alpha || layer -> cfg -> de_type >= SUN8I_MIXER_DE3 ) {
456455 ret = drm_plane_create_alpha_property (& layer -> plane );
457456 if (ret ) {
458457 dev_err (drm -> dev , "Couldn't add alpha property\n" );
@@ -469,7 +468,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
469468
470469 supported_encodings = BIT (DRM_COLOR_YCBCR_BT601 ) |
471470 BIT (DRM_COLOR_YCBCR_BT709 );
472- if (mixer -> cfg -> de_type >= SUN8I_MIXER_DE3 )
471+ if (layer -> cfg -> de_type >= SUN8I_MIXER_DE3 )
473472 supported_encodings |= BIT (DRM_COLOR_YCBCR_BT2020 );
474473
475474 supported_ranges = BIT (DRM_COLOR_YCBCR_LIMITED_RANGE ) |
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