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clk: mediatek: Add MT8196 apmixedsys clock support
Add support for the MT8196 apmixedsys clock controller, which provides PLLs generated from SoC 26m. Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Laura Nao <laura.nao@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎drivers/clk/mediatek/Kconfig‎

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@@ -1002,6 +1002,14 @@ config COMMON_CLK_MT8195_VENCSYS
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help
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This driver supports MediaTek MT8195 vencsys clocks.
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config COMMON_CLK_MT8196
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tristate "Clock driver for MediaTek MT8196"
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depends on ARM64 || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK
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help
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This driver supports MediaTek MT8196 basic clocks.
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config COMMON_CLK_MT8365
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tristate "Clock driver for MediaTek MT8365"
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depends on ARCH_MEDIATEK || COMPILE_TEST

‎drivers/clk/mediatek/Makefile‎

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@@ -150,6 +150,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS) += clk-mt8195-vdo0.o clk-mt8195-vdo1.o
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obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
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obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) += clk-mt8195-vpp0.o clk-mt8195-vpp1.o
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obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
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obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o
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obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
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obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
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obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o

‎drivers/clk/mediatek/clk-mt8196-apmixedsys.c‎

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Guangjie Song <guangjie.song@mediatek.com>
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* Copyright (c) 2025 Collabora Ltd.
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* Laura Nao <laura.nao@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-pll.h"
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/* APMIXEDSYS PLL control register offsets */
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#define MAINPLL_CON0 0x250
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#define MAINPLL_CON1 0x254
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#define UNIVPLL_CON0 0x264
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#define UNIVPLL_CON1 0x268
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#define MSDCPLL_CON0 0x278
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#define MSDCPLL_CON1 0x27c
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#define ADSPPLL_CON0 0x28c
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#define ADSPPLL_CON1 0x290
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#define EMIPLL_CON0 0x2a0
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#define EMIPLL_CON1 0x2a4
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#define EMIPLL2_CON0 0x2b4
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#define EMIPLL2_CON1 0x2b8
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#define NET1PLL_CON0 0x2c8
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#define NET1PLL_CON1 0x2cc
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#define SGMIIPLL_CON0 0x2dc
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#define SGMIIPLL_CON1 0x2e0
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/* APMIXEDSYS_GP2 PLL control register offsets*/
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#define MAINPLL2_CON0 0x250
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#define MAINPLL2_CON1 0x254
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#define UNIVPLL2_CON0 0x264
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#define UNIVPLL2_CON1 0x268
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#define MMPLL2_CON0 0x278
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#define MMPLL2_CON1 0x27c
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#define IMGPLL_CON0 0x28c
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#define IMGPLL_CON1 0x290
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#define TVDPLL1_CON0 0x2a0
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#define TVDPLL1_CON1 0x2a4
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#define TVDPLL2_CON0 0x2b4
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#define TVDPLL2_CON1 0x2b8
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#define TVDPLL3_CON0 0x2c8
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#define TVDPLL3_CON1 0x2cc
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#define PLLEN_ALL 0x080
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#define PLLEN_ALL_SET 0x084
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#define PLLEN_ALL_CLR 0x088
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#define FENC_STATUS_CON0 0x03c
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#define MT8196_PLL_FMAX (3800UL * MHZ)
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#define MT8196_PLL_FMIN (1500UL * MHZ)
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#define MT8196_INTEGER_BITS 8
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#define PLL_FENC(_id, _name, _reg, _fenc_sta_ofs, _fenc_sta_bit,\
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_flags, _pd_reg, _pd_shift, \
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_pcw_reg, _pcw_shift, _pcwbits, \
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_pll_en_bit) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.fenc_sta_ofs = _fenc_sta_ofs, \
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.fenc_sta_bit = _fenc_sta_bit, \
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.flags = _flags, \
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.fmax = MT8196_PLL_FMAX, \
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.fmin = MT8196_PLL_FMIN, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.pcwbits = _pcwbits, \
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.pcwibits = MT8196_INTEGER_BITS, \
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.en_reg = PLLEN_ALL, \
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.en_set_reg = PLLEN_ALL_SET, \
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.en_clr_reg = PLLEN_ALL_CLR, \
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.pll_en_bit = _pll_en_bit, \
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.ops = &mtk_pll_fenc_clr_set_ops, \
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}
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struct mtk_pll_desc {
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const struct mtk_pll_data *clks;
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size_t num_clks;
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};
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static const struct mtk_pll_data apmixed_plls[] = {
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PLL_FENC(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0, FENC_STATUS_CON0,
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7, PLL_AO, MAINPLL_CON1, 24, MAINPLL_CON1, 0, 22, 0),
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PLL_FENC(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0, FENC_STATUS_CON0,
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6, 0, UNIVPLL_CON1, 24, UNIVPLL_CON1, 0, 22, 1),
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PLL_FENC(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0, FENC_STATUS_CON0,
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5, 0, MSDCPLL_CON1, 24, MSDCPLL_CON1, 0, 22, 2),
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PLL_FENC(CLK_APMIXED_ADSPPLL, "adsppll", ADSPPLL_CON0, FENC_STATUS_CON0,
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4, 0, ADSPPLL_CON1, 24, ADSPPLL_CON1, 0, 22, 3),
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PLL_FENC(CLK_APMIXED_EMIPLL, "emipll", EMIPLL_CON0, FENC_STATUS_CON0, 3,
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PLL_AO, EMIPLL_CON1, 24, EMIPLL_CON1, 0, 22, 4),
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PLL_FENC(CLK_APMIXED_EMIPLL2, "emipll2", EMIPLL2_CON0, FENC_STATUS_CON0,
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2, PLL_AO, EMIPLL2_CON1, 24, EMIPLL2_CON1, 0, 22, 5),
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PLL_FENC(CLK_APMIXED_NET1PLL, "net1pll", NET1PLL_CON0, FENC_STATUS_CON0,
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1, 0, NET1PLL_CON1, 24, NET1PLL_CON1, 0, 22, 6),
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PLL_FENC(CLK_APMIXED_SGMIIPLL, "sgmiipll", SGMIIPLL_CON0, FENC_STATUS_CON0,
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0, 0, SGMIIPLL_CON1, 24, SGMIIPLL_CON1, 0, 22, 7),
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};
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static const struct mtk_pll_desc apmixed_desc = {
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.clks = apmixed_plls,
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.num_clks = ARRAY_SIZE(apmixed_plls),
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};
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static const struct mtk_pll_data apmixed2_plls[] = {
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PLL_FENC(CLK_APMIXED2_MAINPLL2, "mainpll2", MAINPLL2_CON0, FENC_STATUS_CON0,
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6, 0, MAINPLL2_CON1, 24, MAINPLL2_CON1, 0, 22, 0),
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PLL_FENC(CLK_APMIXED2_UNIVPLL2, "univpll2", UNIVPLL2_CON0, FENC_STATUS_CON0,
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5, 0, UNIVPLL2_CON1, 24, UNIVPLL2_CON1, 0, 22, 1),
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PLL_FENC(CLK_APMIXED2_MMPLL2, "mmpll2", MMPLL2_CON0, FENC_STATUS_CON0,
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4, 0, MMPLL2_CON1, 24, MMPLL2_CON1, 0, 22, 2),
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PLL_FENC(CLK_APMIXED2_IMGPLL, "imgpll", IMGPLL_CON0, FENC_STATUS_CON0,
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3, 0, IMGPLL_CON1, 24, IMGPLL_CON1, 0, 22, 3),
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PLL_FENC(CLK_APMIXED2_TVDPLL1, "tvdpll1", TVDPLL1_CON0, FENC_STATUS_CON0,
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2, 0, TVDPLL1_CON1, 24, TVDPLL1_CON1, 0, 22, 4),
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PLL_FENC(CLK_APMIXED2_TVDPLL2, "tvdpll2", TVDPLL2_CON0, FENC_STATUS_CON0,
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1, 0, TVDPLL2_CON1, 24, TVDPLL2_CON1, 0, 22, 5),
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PLL_FENC(CLK_APMIXED2_TVDPLL3, "tvdpll3", TVDPLL3_CON0, FENC_STATUS_CON0,
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0, 0, TVDPLL3_CON1, 24, TVDPLL3_CON1, 0, 22, 6),
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};
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static const struct mtk_pll_desc apmixed2_desc = {
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.clks = apmixed2_plls,
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.num_clks = ARRAY_SIZE(apmixed2_plls),
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};
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static int clk_mt8196_apmixed_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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const struct mtk_pll_desc *mcd;
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int r;
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mcd = device_get_match_data(&pdev->dev);
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if (!mcd)
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return -EINVAL;
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clk_data = mtk_alloc_clk_data(mcd->num_clks);
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if (!clk_data)
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return -ENOMEM;
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r = mtk_clk_register_plls(node, mcd->clks, mcd->num_clks, clk_data);
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if (r)
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goto free_apmixed_data;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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goto unregister_plls;
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platform_set_drvdata(pdev, clk_data);
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return r;
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unregister_plls:
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mtk_clk_unregister_plls(mcd->clks, mcd->num_clks, clk_data);
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free_apmixed_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static void clk_mt8196_apmixed_remove(struct platform_device *pdev)
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{
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const struct mtk_pll_desc *mcd = device_get_match_data(&pdev->dev);
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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struct device_node *node = pdev->dev.of_node;
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of_clk_del_provider(node);
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mtk_clk_unregister_plls(mcd->clks, mcd->num_clks, clk_data);
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mtk_free_clk_data(clk_data);
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}
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static const struct of_device_id of_match_clk_mt8196_apmixed[] = {
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{ .compatible = "mediatek,mt8196-apmixedsys", .data = &apmixed_desc },
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{ .compatible = "mediatek,mt8196-apmixedsys-gp2",
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.data = &apmixed2_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_apmixed);
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static struct platform_driver clk_mt8196_apmixed_drv = {
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.probe = clk_mt8196_apmixed_probe,
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.remove = clk_mt8196_apmixed_remove,
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.driver = {
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.name = "clk-mt8196-apmixed",
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.of_match_table = of_match_clk_mt8196_apmixed,
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},
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};
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module_platform_driver(clk_mt8196_apmixed_drv);
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MODULE_DESCRIPTION("MediaTek MT8196 apmixedsys clocks driver");
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MODULE_LICENSE("GPL");

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