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Merge tag 'drm-intel-next-2025-11-14' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
drm/i915 feature pull #2 for v6.19: Features and functionality: - Add initial display support for Xe3p_LPD, display version 35 (Sai Teja, Matt R, Gustavo, Matt A, Ankit, Juha-pekka, Luca, Ravi Kumar) - Compute LT PHY HDMI params when port clock not in predefined tables (Suraj) Refactoring and cleanups: - Refactor intel_frontbuffer split between i915, xe, and display (Ville) - Clean up intel_de_wait_custom() usage (Ville) - Unify display register polling interfaces (Ville) - Finish removal of the expensive format info lookups (Ville) - Cursor code cleanups (Ville) - Convert intel_rom interfaces to struct drm_device (Jani) Fixes: - Fix uninitialized variable in DSI exec packet (Jonathan) - Fix PIPEDMC logging (Alok Tiwari) - Fix PSR pipe to vblank conversion (Jani) - Fix intel_frontbuffer lifetime handling (Ville) - Disable Panel Replay on DP MST for the time being (Imre) Merges: - Backmerge drm-next to get the drm_print.h changes (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/b131309bb7310ab749f1770aa6e36fa8d6a82fa5@intel.com
2 parents 490fd93 + b84befa commit f88f357

83 files changed

Lines changed: 1326 additions & 853 deletions

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‎drivers/gpu/drm/i915/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,7 @@ gem-y += \
156156
gem/i915_gem_lmem.o \
157157
gem/i915_gem_mman.o \
158158
gem/i915_gem_object.o \
159+
gem/i915_gem_object_frontbuffer.o \
159160
gem/i915_gem_pages.o \
160161
gem/i915_gem_phys.o \
161162
gem/i915_gem_pm.o \

‎drivers/gpu/drm/i915/display/hsw_ips.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
5656
* the HW state readout code will complain that the expected
5757
* IPS_CTL value is not the one we read.
5858
*/
59-
if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50))
59+
if (intel_de_wait_for_set_ms(display, IPS_CTL, IPS_ENABLE, 50))
6060
drm_err(display->drm,
6161
"Timed out waiting for IPS enable\n");
6262
}
@@ -78,7 +78,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
7878
* 42ms timeout value leads to occasional timeouts so use 100ms
7979
* instead.
8080
*/
81-
if (intel_de_wait_for_clear(display, IPS_CTL, IPS_ENABLE, 100))
81+
if (intel_de_wait_for_clear_ms(display, IPS_CTL, IPS_ENABLE, 100))
8282
drm_err(display->drm,
8383
"Timed out waiting for IPS disable\n");
8484
} else {

‎drivers/gpu/drm/i915/display/i9xx_plane.c‎

Lines changed: 14 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -754,10 +754,9 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
754754

755755
static unsigned int
756756
hsw_primary_max_stride(struct intel_plane *plane,
757-
u32 pixel_format, u64 modifier,
758-
unsigned int rotation)
757+
const struct drm_format_info *info,
758+
u64 modifier, unsigned int rotation)
759759
{
760-
const struct drm_format_info *info = drm_format_info(pixel_format);
761760
int cpp = info->cpp[0];
762761

763762
/* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */
@@ -766,10 +765,9 @@ hsw_primary_max_stride(struct intel_plane *plane,
766765

767766
static unsigned int
768767
ilk_primary_max_stride(struct intel_plane *plane,
769-
u32 pixel_format, u64 modifier,
770-
unsigned int rotation)
768+
const struct drm_format_info *info,
769+
u64 modifier, unsigned int rotation)
771770
{
772-
const struct drm_format_info *info = drm_format_info(pixel_format);
773771
int cpp = info->cpp[0];
774772

775773
/* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
@@ -781,10 +779,9 @@ ilk_primary_max_stride(struct intel_plane *plane,
781779

782780
unsigned int
783781
i965_plane_max_stride(struct intel_plane *plane,
784-
u32 pixel_format, u64 modifier,
785-
unsigned int rotation)
782+
const struct drm_format_info *info,
783+
u64 modifier, unsigned int rotation)
786784
{
787-
const struct drm_format_info *info = drm_format_info(pixel_format);
788785
int cpp = info->cpp[0];
789786

790787
/* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
@@ -796,8 +793,8 @@ i965_plane_max_stride(struct intel_plane *plane,
796793

797794
static unsigned int
798795
i915_plane_max_stride(struct intel_plane *plane,
799-
u32 pixel_format, u64 modifier,
800-
unsigned int rotation)
796+
const struct drm_format_info *info,
797+
u64 modifier, unsigned int rotation)
801798
{
802799
if (modifier == I915_FORMAT_MOD_X_TILED)
803800
return 8 * 1024;
@@ -807,8 +804,8 @@ i915_plane_max_stride(struct intel_plane *plane,
807804

808805
static unsigned int
809806
i8xx_plane_max_stride(struct intel_plane *plane,
810-
u32 pixel_format, u64 modifier,
811-
unsigned int rotation)
807+
const struct drm_format_info *info,
808+
u64 modifier, unsigned int rotation)
812809
{
813810
if (plane->i9xx_plane == PLANE_C)
814811
return 4 * 1024;
@@ -1191,10 +1188,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
11911188
val = intel_de_read(display, DSPCNTR(display, i9xx_plane));
11921189

11931190
if (DISPLAY_VER(display) >= 4) {
1194-
if (val & DISP_TILED) {
1195-
plane_config->tiling = I915_TILING_X;
1191+
if (val & DISP_TILED)
11961192
fb->modifier = I915_FORMAT_MOD_X_TILED;
1197-
}
11981193

11991194
if (val & DISP_ROTATE_180)
12001195
plane_config->rotation = DRM_MODE_ROTATE_180;
@@ -1206,14 +1201,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
12061201

12071202
pixel_format = val & DISP_FORMAT_MASK;
12081203
fourcc = i9xx_format_to_fourcc(pixel_format);
1209-
fb->format = drm_format_info(fourcc);
1204+
1205+
fb->format = drm_get_format_info(display->drm, fourcc, fb->modifier);
12101206

12111207
if (display->platform.haswell || display->platform.broadwell) {
12121208
offset = intel_de_read(display,
12131209
DSPOFFSET(display, i9xx_plane));
12141210
base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;
12151211
} else if (DISPLAY_VER(display) >= 4) {
1216-
if (plane_config->tiling)
1212+
if (fb->modifier == I915_FORMAT_MOD_X_TILED)
12171213
offset = intel_de_read(display,
12181214
DSPTILEOFF(display, i9xx_plane));
12191215
else

‎drivers/gpu/drm/i915/display/i9xx_plane.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include <linux/types.h>
1010

1111
enum pipe;
12+
struct drm_format_info;
1213
struct drm_framebuffer;
1314
struct intel_crtc;
1415
struct intel_display;
@@ -18,8 +19,8 @@ struct intel_plane_state;
1819

1920
#ifdef I915
2021
unsigned int i965_plane_max_stride(struct intel_plane *plane,
21-
u32 pixel_format, u64 modifier,
22-
unsigned int rotation);
22+
const struct drm_format_info *info,
23+
u64 modifier, unsigned int rotation);
2324
unsigned int vlv_plane_min_alignment(struct intel_plane *plane,
2425
const struct drm_framebuffer *fb,
2526
int colot_plane);

‎drivers/gpu/drm/i915/display/icl_dsi.c‎

Lines changed: 16 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -148,9 +148,9 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
148148
for_each_dsi_port(port, intel_dsi->ports) {
149149
dsi_trans = dsi_port_to_transcoder(port);
150150

151-
ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),
152-
LPTX_IN_PROGRESS, 0,
153-
20, 0, NULL);
151+
ret = intel_de_wait_for_clear_us(display,
152+
DSI_LP_MSG(dsi_trans),
153+
LPTX_IN_PROGRESS, 20);
154154
if (ret)
155155
drm_err(display->drm, "LPTX bit not cleared\n");
156156
}
@@ -534,9 +534,8 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
534534
for_each_dsi_port(port, intel_dsi->ports) {
535535
intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
536536

537-
ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),
538-
DDI_BUF_IS_IDLE, 0,
539-
500, 0, NULL);
537+
ret = intel_de_wait_for_clear_us(display, DDI_BUF_CTL(port),
538+
DDI_BUF_IS_IDLE, 500);
540539
if (ret)
541540
drm_err(display->drm, "DDI port:%c buffer idle\n",
542541
port_name(port));
@@ -857,9 +856,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
857856

858857
dsi_trans = dsi_port_to_transcoder(port);
859858

860-
ret = intel_de_wait_custom(display, DSI_TRANS_FUNC_CONF(dsi_trans),
861-
LINK_READY, LINK_READY,
862-
2500, 0, NULL);
859+
ret = intel_de_wait_for_set_us(display,
860+
DSI_TRANS_FUNC_CONF(dsi_trans),
861+
LINK_READY, 2500);
863862
if (ret)
864863
drm_err(display->drm, "DSI link not ready\n");
865864
}
@@ -1048,8 +1047,8 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
10481047
TRANSCONF_ENABLE);
10491048

10501049
/* wait for transcoder to be enabled */
1051-
if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),
1052-
TRANSCONF_STATE_ENABLE, 10))
1050+
if (intel_de_wait_for_set_ms(display, TRANSCONF(display, dsi_trans),
1051+
TRANSCONF_STATE_ENABLE, 10))
10531052
drm_err(display->drm,
10541053
"DSI transcoder not enabled\n");
10551054
}
@@ -1317,8 +1316,8 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
13171316
TRANSCONF_ENABLE, 0);
13181317

13191318
/* wait for transcoder to be disabled */
1320-
if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),
1321-
TRANSCONF_STATE_ENABLE, 50))
1319+
if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, dsi_trans),
1320+
TRANSCONF_STATE_ENABLE, 50))
13221321
drm_err(display->drm,
13231322
"DSI trancoder not disabled\n");
13241323
}
@@ -1358,9 +1357,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
13581357
tmp &= ~LINK_ULPS_TYPE_LP11;
13591358
intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
13601359

1361-
ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),
1362-
LINK_IN_ULPS, LINK_IN_ULPS,
1363-
10, 0, NULL);
1360+
ret = intel_de_wait_for_set_us(display, DSI_LP_MSG(dsi_trans),
1361+
LINK_IN_ULPS, 10);
13641362
if (ret)
13651363
drm_err(display->drm, "DSI link not in ULPS\n");
13661364
}
@@ -1395,9 +1393,8 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
13951393
for_each_dsi_port(port, intel_dsi->ports) {
13961394
intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
13971395

1398-
ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),
1399-
DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE,
1400-
8, 0, NULL);
1396+
ret = intel_de_wait_for_set_us(display, DDI_BUF_CTL(port),
1397+
DDI_BUF_IS_IDLE, 8);
14011398

14021399
if (ret)
14031400
drm_err(display->drm,

‎drivers/gpu/drm/i915/display/intel_bios.c‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@
3636

3737
#include "soc/intel_rom.h"
3838

39-
#include "i915_drv.h"
4039
#include "intel_display.h"
4140
#include "intel_display_core.h"
4241
#include "intel_display_rpm.h"
@@ -3145,7 +3144,6 @@ static struct vbt_header *oprom_get_vbt(struct intel_display *display,
31453144
static const struct vbt_header *intel_bios_get_vbt(struct intel_display *display,
31463145
size_t *sizep)
31473146
{
3148-
struct drm_i915_private *i915 = to_i915(display->drm);
31493147
const struct vbt_header *vbt = NULL;
31503148

31513149
vbt = firmware_get_vbt(display, sizep);
@@ -3159,11 +3157,11 @@ static const struct vbt_header *intel_bios_get_vbt(struct intel_display *display
31593157
*/
31603158
if (!vbt && display->platform.dgfx)
31613159
with_intel_display_rpm(display)
3162-
vbt = oprom_get_vbt(display, intel_rom_spi(i915), sizep, "SPI flash");
3160+
vbt = oprom_get_vbt(display, intel_rom_spi(display->drm), sizep, "SPI flash");
31633161

31643162
if (!vbt)
31653163
with_intel_display_rpm(display)
3166-
vbt = oprom_get_vbt(display, intel_rom_pci(i915), sizep, "PCI ROM");
3164+
vbt = oprom_get_vbt(display, intel_rom_pci(display->drm), sizep, "PCI ROM");
31673165

31683166
return vbt;
31693167
}

‎drivers/gpu/drm/i915/display/intel_bo.c‎

Lines changed: 30 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -29,11 +29,6 @@ bool intel_bo_is_protected(struct drm_gem_object *obj)
2929
return i915_gem_object_is_protected(to_intel_bo(obj));
3030
}
3131

32-
void intel_bo_flush_if_display(struct drm_gem_object *obj)
33-
{
34-
i915_gem_object_flush_if_display(to_intel_bo(obj));
35-
}
36-
3732
int intel_bo_fb_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
3833
{
3934
return i915_gem_fb_mmap(to_intel_bo(obj), vma);
@@ -44,15 +39,40 @@ int intel_bo_read_from_page(struct drm_gem_object *obj, u64 offset, void *dst, i
4439
return i915_gem_object_read_from_page(to_intel_bo(obj), offset, dst, size);
4540
}
4641

47-
struct intel_frontbuffer *intel_bo_get_frontbuffer(struct drm_gem_object *obj)
42+
struct intel_frontbuffer *intel_bo_frontbuffer_get(struct drm_gem_object *_obj)
43+
{
44+
struct drm_i915_gem_object *obj = to_intel_bo(_obj);
45+
struct i915_frontbuffer *front;
46+
47+
front = i915_gem_object_frontbuffer_get(obj);
48+
if (!front)
49+
return NULL;
50+
51+
return &front->base;
52+
}
53+
54+
void intel_bo_frontbuffer_ref(struct intel_frontbuffer *_front)
4855
{
49-
return i915_gem_object_get_frontbuffer(to_intel_bo(obj));
56+
struct i915_frontbuffer *front =
57+
container_of(_front, typeof(*front), base);
58+
59+
i915_gem_object_frontbuffer_ref(front);
5060
}
5161

52-
struct intel_frontbuffer *intel_bo_set_frontbuffer(struct drm_gem_object *obj,
53-
struct intel_frontbuffer *front)
62+
void intel_bo_frontbuffer_put(struct intel_frontbuffer *_front)
5463
{
55-
return i915_gem_object_set_frontbuffer(to_intel_bo(obj), front);
64+
struct i915_frontbuffer *front =
65+
container_of(_front, typeof(*front), base);
66+
67+
return i915_gem_object_frontbuffer_put(front);
68+
}
69+
70+
void intel_bo_frontbuffer_flush_for_display(struct intel_frontbuffer *_front)
71+
{
72+
struct i915_frontbuffer *front =
73+
container_of(_front, typeof(*front), base);
74+
75+
i915_gem_object_flush_if_display(front->obj);
5676
}
5777

5878
void intel_bo_describe(struct seq_file *m, struct drm_gem_object *obj)

‎drivers/gpu/drm/i915/display/intel_bo.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,13 +16,13 @@ bool intel_bo_is_tiled(struct drm_gem_object *obj);
1616
bool intel_bo_is_userptr(struct drm_gem_object *obj);
1717
bool intel_bo_is_shmem(struct drm_gem_object *obj);
1818
bool intel_bo_is_protected(struct drm_gem_object *obj);
19-
void intel_bo_flush_if_display(struct drm_gem_object *obj);
2019
int intel_bo_fb_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
2120
int intel_bo_read_from_page(struct drm_gem_object *obj, u64 offset, void *dst, int size);
2221

23-
struct intel_frontbuffer *intel_bo_get_frontbuffer(struct drm_gem_object *obj);
24-
struct intel_frontbuffer *intel_bo_set_frontbuffer(struct drm_gem_object *obj,
25-
struct intel_frontbuffer *front);
22+
struct intel_frontbuffer *intel_bo_frontbuffer_get(struct drm_gem_object *obj);
23+
void intel_bo_frontbuffer_ref(struct intel_frontbuffer *front);
24+
void intel_bo_frontbuffer_put(struct intel_frontbuffer *front);
25+
void intel_bo_frontbuffer_flush_for_display(struct intel_frontbuffer *front);
2626

2727
void intel_bo_describe(struct seq_file *m, struct drm_gem_object *obj);
2828

‎drivers/gpu/drm/i915/display/intel_bw.c‎

Lines changed: 27 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -805,29 +805,40 @@ void intel_bw_init_hw(struct intel_display *display)
805805
if (!HAS_DISPLAY(display))
806806
return;
807807

808-
if (DISPLAY_VERx100(display) >= 3002)
809-
tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
810-
else if (DISPLAY_VER(display) >= 30)
811-
tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
812-
else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx &&
813-
dram_info->type == INTEL_DRAM_GDDR_ECC)
814-
xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
815-
else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)
816-
xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
817-
else if (DISPLAY_VER(display) >= 14)
808+
/*
809+
* Starting with Xe3p_LPD, the hardware tells us whether memory has ECC
810+
* enabled that would impact display bandwidth. However, so far there
811+
* are no instructions in Bspec on how to handle that case. Let's
812+
* complain if we ever find such a scenario.
813+
*/
814+
if (DISPLAY_VER(display) >= 35)
815+
drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
816+
817+
if (DISPLAY_VER(display) >= 30) {
818+
if (DISPLAY_VERx100(display) == 3002)
819+
tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
820+
else
821+
tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
822+
} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
823+
if (dram_info->type == INTEL_DRAM_GDDR_ECC)
824+
xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
825+
else
826+
xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
827+
} else if (DISPLAY_VER(display) >= 14) {
818828
tgl_get_bw_info(display, dram_info, &mtl_sa_info);
819-
else if (display->platform.dg2)
829+
} else if (display->platform.dg2) {
820830
dg2_get_bw_info(display);
821-
else if (display->platform.alderlake_p)
831+
} else if (display->platform.alderlake_p) {
822832
tgl_get_bw_info(display, dram_info, &adlp_sa_info);
823-
else if (display->platform.alderlake_s)
833+
} else if (display->platform.alderlake_s) {
824834
tgl_get_bw_info(display, dram_info, &adls_sa_info);
825-
else if (display->platform.rocketlake)
835+
} else if (display->platform.rocketlake) {
826836
tgl_get_bw_info(display, dram_info, &rkl_sa_info);
827-
else if (DISPLAY_VER(display) == 12)
837+
} else if (DISPLAY_VER(display) == 12) {
828838
tgl_get_bw_info(display, dram_info, &tgl_sa_info);
829-
else if (DISPLAY_VER(display) == 11)
839+
} else if (DISPLAY_VER(display) == 11) {
830840
icl_get_bw_info(display, dram_info, &icl_sa_info);
841+
}
831842
}
832843

833844
static unsigned int intel_bw_num_active_planes(struct intel_display *display,

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