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phy: apple: atc: Add t8122 thunderbolt support. #574

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111 changes: 62 additions & 49 deletions drivers/phy/apple/atc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -595,7 +595,10 @@ struct atcphy_mode_configuration {
bool set_swap;
};

struct apple_atcphy;

struct atcphy_hw {
void (*configure_post_tunable)(struct apple_atcphy *, enum atcphy_mode);
enum atcphy_generation gen;
int aciophy_lane_mode;
int aciophy_crossbar;
Expand Down Expand Up @@ -1312,7 +1315,7 @@ static void atcphy_configure_lanes(struct apple_atcphy *atcphy, enum atcphy_mode
core_clear32(atcphy, atcphy->hw->aciophy_crossbar, ACIOPHY_CROSSBAR_DP_BOTH_PMA);

/* unclear if we need the remainder for t8122 */
if (atcphy->hw->gen == ATCPHY_GENERATION_T8122)
if (atcphy->hw->gen == ATCPHY_GENERATION_T8122)
return;

if (mode_cfg->dp_lane[0]) {
Expand Down Expand Up @@ -1863,6 +1866,59 @@ static int atcphy_power_on(struct apple_atcphy *atcphy)
return 0;
}

static void atcphy_configure_post_tunable_t8103(struct apple_atcphy *atcphy, enum atcphy_mode _mode)
{
core_set32(atcphy, AUSPLL_FSM_CTRL, 0x1fe000);
core_set32(atcphy, AUSPLL_APB_CMD_OVERRIDE, AUSPLL_APB_CMD_OVERRIDE_UNK28);

set32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_SMALL_OV);
udelay(10);
set32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_BIG_OV);
udelay(10);
set32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_CLAMP_OV);
udelay(10);

mask32(atcphy->regs.core + ACIOPHY_SLEEP_CTRL, ACIOPHY_SLEEP_CTRL_TX_SMALL_OV,
FIELD_PREP(ACIOPHY_SLEEP_CTRL_TX_SMALL_OV, 3));
udelay(10);
mask32(atcphy->regs.core + ACIOPHY_SLEEP_CTRL, ACIOPHY_SLEEP_CTRL_TX_BIG_OV,
FIELD_PREP(ACIOPHY_SLEEP_CTRL_TX_BIG_OV, 3));
udelay(10);
mask32(atcphy->regs.core + ACIOPHY_SLEEP_CTRL, ACIOPHY_SLEEP_CTRL_TX_CLAMP_OV,
FIELD_PREP(ACIOPHY_SLEEP_CTRL_TX_CLAMP_OV, 3));
udelay(10);

mask32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_RX_BIG_OV,
FIELD_PREP(ACIOPHY_CFG0_RX_BIG_OV, 3));
udelay(10);
mask32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_RX_SMALL_OV,
FIELD_PREP(ACIOPHY_CFG0_RX_SMALL_OV, 3));
udelay(10);
mask32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_RX_CLAMP_OV,
FIELD_PREP(ACIOPHY_CFG0_RX_CLAMP_OV, 3));
udelay(10);
}

static void atcphy_configure_post_tunable_t8122(struct apple_atcphy *atcphy, enum atcphy_mode mode)
{
if (atcphy_modes[mode].pipehandler_state != ATCPHY_PIPEHANDLER_STATE_USB3)
return;
core_set32(atcphy, ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_SMALL);
udelay(10);
core_set32(atcphy, ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_SMALL_OV);
udelay(10);
core_set32(atcphy, ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_BIG);
udelay(10);
core_set32(atcphy, ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_BIG_OV);
udelay(10);
core_clear32(atcphy, ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_CLAMP);
udelay(10);
core_set32(atcphy, ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_CLAMP_OV);
udelay(10);
core_set32(atcphy, AUS_COMMON_SHIM_BLK_BIAS_REG, AUS_COMMON_SHIM_BLK_BIAS_REG_BGBIAS_OV);
udelay(10);
}

static int atcphy_configure(struct apple_atcphy *atcphy, enum atcphy_mode mode)
{
int ret = 0;
Expand All @@ -1881,53 +1937,7 @@ static int atcphy_configure(struct apple_atcphy *atcphy, enum atcphy_mode mode)
return ret;

atcphy_apply_tunables(atcphy, mode);

if (atcphy->hw->gen == ATCPHY_GENERATION_T8103) {
core_set32(atcphy, AUSPLL_FSM_CTRL, 0x1fe000);
core_set32(atcphy, AUSPLL_APB_CMD_OVERRIDE, AUSPLL_APB_CMD_OVERRIDE_UNK28);

set32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_SMALL_OV);
udelay(10);
set32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_BIG_OV);
udelay(10);
set32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_CLAMP_OV);
udelay(10);

mask32(atcphy->regs.core + ACIOPHY_SLEEP_CTRL, ACIOPHY_SLEEP_CTRL_TX_SMALL_OV,
FIELD_PREP(ACIOPHY_SLEEP_CTRL_TX_SMALL_OV, 3));
udelay(10);
mask32(atcphy->regs.core + ACIOPHY_SLEEP_CTRL, ACIOPHY_SLEEP_CTRL_TX_BIG_OV,
FIELD_PREP(ACIOPHY_SLEEP_CTRL_TX_BIG_OV, 3));
udelay(10);
mask32(atcphy->regs.core + ACIOPHY_SLEEP_CTRL, ACIOPHY_SLEEP_CTRL_TX_CLAMP_OV,
FIELD_PREP(ACIOPHY_SLEEP_CTRL_TX_CLAMP_OV, 3));
udelay(10);

mask32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_RX_BIG_OV,
FIELD_PREP(ACIOPHY_CFG0_RX_BIG_OV, 3));
udelay(10);
mask32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_RX_SMALL_OV,
FIELD_PREP(ACIOPHY_CFG0_RX_SMALL_OV, 3));
udelay(10);
mask32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_RX_CLAMP_OV,
FIELD_PREP(ACIOPHY_CFG0_RX_CLAMP_OV, 3));
udelay(10);
} else if (atcphy->hw->gen == ATCPHY_GENERATION_T8122) {
core_set32(atcphy, ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_SMALL);
udelay(10);
core_set32(atcphy, ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_SMALL_OV);
udelay(10);
core_set32(atcphy, ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_BIG);
udelay(10);
core_set32(atcphy, ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_BIG_OV);
udelay(10);
core_clear32(atcphy, ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_CLAMP);
udelay(10);
core_set32(atcphy, ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_CLAMP_OV);
udelay(10);
core_set32(atcphy, AUS_COMMON_SHIM_BLK_BIAS_REG, AUS_COMMON_SHIM_BLK_BIAS_REG_BGBIAS_OV);
udelay(10);
}
atcphy->hw->configure_post_tunable(atcphy, mode);

/* Setup AUX channel if DP altmode is requested */
if (atcphy_modes[mode].enable_dp_aux)
Expand All @@ -1947,7 +1957,8 @@ static int atcphy_configure(struct apple_atcphy *atcphy, enum atcphy_mode mode)
* does lane configuration with phy out of reset, and the poll is right after AUS_COMMON_SHIM_BLK_BIAS_REG
* write. Does not seem to matter, but if something does not work, consider re-ordering things to macos order.
*/
if (atcphy->hw->gen == ATCPHY_GENERATION_T8122) {
if (atcphy->hw->gen == ATCPHY_GENERATION_T8122 &&
atcphy_modes[mode].pipehandler_state == ATCPHY_PIPEHANDLER_STATE_USB3) {
ret = readl_poll_timeout(atcphy->regs.core + AUS_COMMON_DIG_RCAL1, reg,
(reg & AUS_COMMON_DIG_RCAL1_ALL_CODES_DONE), 10, 100000);
if (ret) {
Expand Down Expand Up @@ -2485,12 +2496,14 @@ static const struct atcphy_hw atcphy_hw_t8103 = {
.gen = ATCPHY_GENERATION_T8103,
.aciophy_lane_mode = ACIOPHY_LANE_MODE_T8103,
.aciophy_crossbar = ACIOPHY_CROSSBAR_T8103,
.configure_post_tunable = atcphy_configure_post_tunable_t8103,
};

static const struct atcphy_hw atcphy_hw_t8122 = {
.gen = ATCPHY_GENERATION_T8122,
.aciophy_lane_mode = ACIOPHY_LANE_MODE_T8122,
.aciophy_crossbar = ACIOPHY_CROSSBAR_T8122,
.configure_post_tunable = atcphy_configure_post_tunable_t8122,
};

static const struct of_device_id atcphy_match[] = {
Expand Down