Support launch bounds on the GCN target - #918
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minthreads/maxthreads on GCNCompilerTarget emit amdgpu-flat-work-group-sizes, mirroring the PTX target's fields. Without the attribute the backend budgets registers for 1024-item workgroups. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
maleadt
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Aug 28, 2026
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The GCN target compiles every kernel with the backend's default
amdgpu-flat-work-group-sizeof1,1024, so the register allocator always budgets for 1024-item workgroups: on gfx942 that is a 128-VGPR cap, and register-heavy kernels spill even when they will only ever be launched with smaller workgroups. HIP C++ exposes this via__launch_bounds__; the PTX target already exposes it asminthreads/maxthreads.This adds the same two fields to
GCNCompilerTarget, emitted asamdgpu-flat-work-group-sizeon kernels. LLVM derives the minimum waves/EU from the attribute's maximum (AMDGPUSubtarget::getEffectiveWavesPerEU), which sets the VGPR budget (GCNSubtarget::getBaseMaxNumVGPRs).Measured on MI300A (gfx942, ROCm 7.2.4, Julia 1.12) with a register-tiled FP32 GEMM from AMDGPU.jl (16×16 workgroup, 8×8 accumulator microtile per thread, 4096³):
maxthreads=256A companion AMDGPU.jl PR plumbs this through
@roc maxthreads=and sets it automatically for KernelAbstractions kernels with static workgroup sizes, mirroring CUDA.jl. As a bonus the bound lands in the code object's.max_flat_workgroup_size, so HIP itself rejects out-of-bounds launches that were previously silent UB.🤖 Generated with Claude Code