mesa-7i65: fix a bug with stale data in fifo

Writing to BSPI channels with echo enabled also simultaneously reads from
those channels.  The read bytes go into the BSPI instance's read fifo,
where they stay until the driver reads them out.

By writing to the (echo-y) ADCs to configure them, we also put some
bytes into the read fifo.  When we later try to read the analog and
digital inputs, we'll actually get the old bytes from the ADC setup,
and everything will be off by a handful of bytes, resulting in incorrect
information being used.

This commit fixes the problem by clearing the FIFO after setting up
the ADCs.

There may be another bug lurking in here - if somehow the FIFO becomes
out of sync, we'll never recover.  A future hacker will get the pleasure
of rediscovering this problem and fixing it.

Author: SebKuzminsky

src/hal/drivers/mesa_7i65.comp

@@ -206,6 +206,15 @@ EXTRA_SETUP(){
                       "quitting\n", -r);
         return -EINVAL;
     }
+
+    // Clear BSPI Rx & Tx FIFOs.
+    // This discards the received data from the ADC setup writes above,
+    // and any other old stale data.
+    r = hm2_bspi_clear_fifo(name);
+    if (r < 0) {
+        rtapi_print_msg(RTAPI_MSG_ERR, "failed to clear BSPI fifos on %s\n", name);
+    }
+
     // Add BSPI Frames
     r += hm2_tram_add_bspi_frame(name, 4, &CPLD_write,
                             &CPLD_read);