fix(fpga_diff): correct JTAG flash burst order

[klin02]

Summary

Vivado assigns the rightmost data beat to the lowest address of an INCR transaction. Pack each flash burst in reverse textual order so binary words retain ascending memory addresses.

The byte order within each 32-bit word is unchanged.

Validation

• ran the complete Tcl writer with mocked Vivado hardware commands
• wrote the 10068-byte bootrom-noprint.bin using 256-word bursts
• passed first, middle, and final sample readback checks
• confirmed address 0x10000000 contains the first instruction 0x00000413