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1 parent 33f8aff commit 315ec5bCopy full SHA for 315ec5b
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bsp/xuantie/virt64/c906/libcpu/riscv_mmu.h
@@ -18,6 +18,18 @@
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#undef PAGE_SIZE
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+/*
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+ * RISC-V Standard Svpbmt Extension (Bit 61-62)
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+ * 00: PMA (Normal Memory, Cacheable, No change to implied PMA memory type)
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+ * 01: NC (Non-cacheable, Weakly-ordered)
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+ * 10: IO (Strongly-ordered, Non-cacheable, Non-idempotent)
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+ * 11: Reserved
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+ */
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+#define PTE_PBMT_PMA (0UL << 61)
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+#define PTE_PBMT_NC (1UL << 61)
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+#define PTE_PBMT_IO (2UL << 61)
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+#define PTE_PBMT_MASK (3UL << 61)
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+
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#define PAGE_OFFSET_SHIFT 0
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#define PAGE_OFFSET_BIT 12
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#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
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