feat[STM32][I2C]: add timing control support for hard i2c

[wdfk-prog]

拉取/合并请求描述：(PR description)

[

为什么提交这份PR (why to submit this PR)

当前 STM32 硬件 I2C 驱动对不同代际 I2C IP 的 timing 语义处理不一致：

• legacy I2C IP（如 F1/F4）实际通过 ClockSpeed/DutyCycle 进行配置，但部分配置项中使用了原始寄存器风格的 timing 值；
• TIMINGR-based I2C IP（如 F7/H7）则需要使用原始 TIMINGR 值；
• 驱动中此前若干逻辑主要按 H7 分支处理，不利于扩展到其他 TIMINGR-based 平台；
• 同时，legacy IP 缺少统一的运行时 timing 调整入口。

因此，这个 PR 主要用于统一 STM32 硬件 I2C 的 timing 语义处理方式，按 I2C IP 代际区分配置逻辑，并补充 legacy IP 的 timing control 支持。

你的解决方案是什么 (what is your solution)

本次改动主要包括：

1. 在 drv_hard_i2c.h 中增加 STM32_I2C_LEGACY_IP 和 STM32_I2C_TIMINGR_IP 分类宏，明确 timing 字段语义：

   • legacy IP：timing 表示总线频率（Hz）
   • TIMINGR IP：timing 表示原始 TIMINGR 寄存器值

2. 在 drv_hard_i2c.c 中新增默认 timing 处理逻辑：

   • legacy IP 默认值为 100000
   • TIMINGR IP 默认值为默认 TIMINGR 常量
   • 在初始化前统一补全默认配置，避免 timing == 0 时行为不确定

3. 调整 I2C 初始化逻辑：

   • legacy IP 使用 cfg->timing 配置 ClockSpeed
   • TIMINGR IP 使用 cfg->timing 配置 Init.Timing
   • 原先仅针对 H7 的若干条件分支改为按 I2C IP 代际统一分支

4. 为 legacy IP 增加 BSP_I2C_CTRL_SET_TIMING 控制命令：

   • 支持在运行时设置 timing
   • 同步更新 usage_freq / max_hz
   • 重新配置总线参数

5. 更新系列配置头文件：

   • F1/F4 的 timing 配置改为 100000
   • 新增 F7 i2c_hard_config.h，继续使用 TIMINGR 配置方式

6. 调整超时和错误处理逻辑：

   • legacy IP 继续基于 usage_freq 估算传输超时
   • TIMINGR IP 使用 bus timeout 配置
   • STOP/NACK/BERR 相关处理从仅 H7 扩展为所有 TIMINGR-based I2C IP 通用逻辑

7. 顺带修正 DMA RX 初始化中 FIFO/Burst 参数误写到 TX handle 的问题

请提供验证的bsp和config (provide the config and bsp)

• BSP:

  • [请填写实际验证的 BSP 路径，例如 bsp/stm32/...]

• .config:

  • [请填写验证该 PR 时使用的 I2C / DMA 相关配置，例如 BSP_USING_HARD_I2C1、BSP_I2C1_RX_USING_DMA 等]

• action:

  • [请填写你自己仓库 PR branch 对应的 action 链接]

]

当前拉取/合并请求的状态 Intent for your PR

必须选择一项 Choose one (Mandatory):

• 本拉取/合并请求是一个草稿版本 This PR is for a code-review and is intended to get feedback
• 本拉取/合并请求是一个成熟版本 This PR is mature, and ready to be integrated into the repo

代码质量 Code Quality：

我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:

• 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
• 代码风格正确，包括缩进空格，命名及其他风格 Style guide is adhered to, including spacing, naming and other styles
• 没有垃圾代码，代码尽量精简，不包含#if 0代码，不包含已经被注释了的代码 All redundant code is removed and cleaned up
• 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
• 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
• 代码是高质量的 Code in this PR is of high quality
• 已经使用formatting 等源码格式化工具确保格式符合RT-Thread代码规范 This PR complies with RT-Thread code specification
• 如果是新增bsp, 已经添加ci检查到.github/ALL_BSP_COMPILE.json 详细请参考链接BSP自查

[github-actions]

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[github-actions]

📌 Code Review Assignment

🏷️ Tag: bsp_stm32

Reviewers: Liang1795 hamburger-os wdfk-prog

Changed Files (Click to expand)

• bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/i2c_hard_config.h
• bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h
• bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c
• bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h

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📊 Current Review Status (Last Updated: 2026-04-13 11:45 CST)

• ⌛ Liang1795 Pending Review
• ⌛ hamburger-os Pending Review
• ⌛ wdfk-prog Pending Review

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[Copilot]

Pull request overview

This PR updates the STM32 hardware I2C driver to clarify and standardize the meaning of the timing configuration field based on the underlying I2C IP generation (legacy vs TIMINGR-based), and adds a runtime timing-control entry for legacy IPs. It also aligns BSP config defaults accordingly and fixes a DMA RX initialization assignment issue.

Changes:

• Split timing semantics by I2C IP generation (legacy: Hz; TIMINGR-based: raw TIMINGR value) and apply defaults when timing == 0.
• Add legacy-only bus control command to update timing at runtime, and initialize legacy bus max_hz/usage_freq from timing.
• Update F1/F4 timing configs to 100000 (Hz) and add a new F7 hard-I2C config using TIMINGR values; fix DMA RX FIFO/Burst init assignments.

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 7 comments.

Show a summary per file

File	Description
bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h	Introduces IP-generation macros and documents/defines timing semantics and control command.
bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c	Applies default timing, adjusts init paths per IP generation, updates timeout/error handling behavior, adds legacy timing control, and fixes DMA RX init fields.
bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/i2c_hard_config.h	Adds F7 hard-I2C configuration using TIMINGR timing values.
bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h	Updates legacy timing values to be bus frequency in Hz.
bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/i2c_hard_config.h	Adds legacy timing values (Hz) for F1 configs.