Skip to content

Commit 0039848

Browse files
Marek VasutShawn Guo
Marek Vasut
authored and
Shawn Guo
committed
arm64: dts: imx8mp: Update Data Modul i.MX8M Plus eDM SBC DT to rev.903
Update the DT to match newest Data Modul i.MX8M Plus eDM SBC rev.903 board which implements significant changes. Keep some of the rev.900 and rev.902 nodes in the DT so that a DTO can be used to support old rev.900 and rev.902 boards easily. The changes from rev.900 to rev.902 are: - Both ethernet PHYs replaced from AR8031 to BCM54213PE - Both ethernet PHYs MDIO address changed - PCIe WiFi now comes with dedicated regulator - I2C TPM chip address - Additional GPIO expander for LVDS panel control added - Current EEPROM I2C address changed - Another optional EEPROM added onto another I2C bus The changes from rev.902 to rev.903 are: - Additional GPIO expander for WiFi and LVDS panel control added - Multiple GPIOs are reassigned Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
1 parent 6f6c18c commit 0039848

1 file changed

Lines changed: 129 additions & 19 deletions

File tree

‎arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts‎

Lines changed: 129 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,17 @@
9393
status = "disabled";
9494
};
9595

96+
reg_pcie0: regulator-pcie {
97+
compatible = "regulator-fixed";
98+
pinctrl-names = "default";
99+
pinctrl-0 = <&pinctrl_wifi>;
100+
regulator-name = "WIFI_BT_RST#";
101+
regulator-min-microvolt = <3300000>;
102+
regulator-max-microvolt = <3300000>;
103+
gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
104+
enable-active-high;
105+
};
106+
96107
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
97108
compatible = "regulator-fixed";
98109
pinctrl-names = "default";
@@ -190,7 +201,7 @@
190201
&eqos { /* First ethernet */
191202
pinctrl-names = "default";
192203
pinctrl-0 = <&pinctrl_eqos>;
193-
phy-handle = <&phy_eqos>;
204+
phy-handle = <&phy_eqos_bcm>;
194205
phy-mode = "rgmii-id";
195206
status = "okay";
196207

@@ -200,7 +211,7 @@
200211
#size-cells = <0>;
201212

202213
/* Atheros AR8031 PHY */
203-
phy_eqos: ethernet-phy@0 {
214+
phy_eqos_ath: ethernet-phy@0 {
204215
compatible = "ethernet-phy-ieee802.3-c22";
205216
reg = <0>;
206217
/*
@@ -213,6 +224,7 @@
213224
reset-deassert-us = <10000>;
214225
qca,keep-pll-enabled;
215226
vddio-supply = <&vddio_eqos>;
227+
status = "disabled";
216228

217229
vddio_eqos: vddio-regulator {
218230
regulator-name = "VDDIO_EQOS";
@@ -224,13 +236,27 @@
224236
regulator-name = "VDDH_EQOS";
225237
};
226238
};
239+
240+
/* Broadcom BCM54213PE PHY */
241+
phy_eqos_bcm: ethernet-phy@1 {
242+
compatible = "ethernet-phy-ieee802.3-c22";
243+
reg = <1>;
244+
/*
245+
* Dedicated ENET_INT# and ENET_WOL# signals are
246+
* unused, the PHY does not provide cable detect
247+
* interrupt.
248+
*/
249+
reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
250+
reset-assert-us = <10000>;
251+
reset-deassert-us = <10000>;
252+
};
227253
};
228254
};
229255

230256
&fec { /* Second ethernet */
231257
pinctrl-names = "default";
232258
pinctrl-0 = <&pinctrl_fec>;
233-
phy-handle = <&phy_fec>;
259+
phy-handle = <&phy_fec_bcm>;
234260
phy-mode = "rgmii-id";
235261
fsl,magic-packet;
236262
status = "okay";
@@ -240,7 +266,7 @@
240266
#size-cells = <0>;
241267

242268
/* Atheros AR8031 PHY */
243-
phy_fec: ethernet-phy@0 {
269+
phy_fec_ath: ethernet-phy@0 {
244270
compatible = "ethernet-phy-ieee802.3-c22";
245271
reg = <0>;
246272
/*
@@ -253,6 +279,7 @@
253279
reset-deassert-us = <10000>;
254280
qca,keep-pll-enabled;
255281
vddio-supply = <&vddio_fec>;
282+
status = "disabled";
256283

257284
vddio_fec: vddio-regulator {
258285
regulator-name = "VDDIO_FEC";
@@ -264,6 +291,20 @@
264291
regulator-name = "VDDH_FEC";
265292
};
266293
};
294+
295+
/* Broadcom BCM54213PE PHY */
296+
phy_fec_bcm: ethernet-phy@1 {
297+
compatible = "ethernet-phy-ieee802.3-c22";
298+
reg = <1>;
299+
/*
300+
* Dedicated ENET_INT# and ENET_WOL# signals are
301+
* unused, the PHY does not provide cable detect
302+
* interrupt.
303+
*/
304+
reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
305+
reset-assert-us = <10000>;
306+
reset-deassert-us = <10000>;
307+
};
267308
};
268309
};
269310

@@ -378,13 +419,26 @@
378419
self-powered;
379420
};
380421

381-
eeprom: eeprom@50 {
422+
tpm: tpm@2e {
423+
compatible = "st,st33tphf2ei2c", "tcg,tpm-tis-i2c";
424+
reg = <0x2e>;
425+
};
426+
427+
eeprom900: eeprom@50 { /* board rev.900 */
382428
compatible = "atmel,24c32";
383429
reg = <0x50>;
384430
pagesize = <32>;
431+
status = "disabled";
432+
};
433+
434+
eeprom902: eeprom@51 { /* board rev.902 */
435+
compatible = "atmel,24c32";
436+
reg = <0x51>;
437+
pagesize = <32>;
385438
};
386439

387440
rtc: rtc@68 {
441+
#clock-cells = <1>;
388442
compatible = "st,m41t62";
389443
reg = <0x68>;
390444
pinctrl-names = "default";
@@ -408,6 +462,46 @@
408462
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
409463
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
410464
status = "okay";
465+
466+
gpiolvds: io-expander@20 {
467+
compatible = "nxp,pca9554";
468+
reg = <0x20>;
469+
gpio-controller;
470+
#gpio-cells = <2>;
471+
gpio-line-names =
472+
"BL_ENABLE_V", "SEL_BL_12V",
473+
"SEL_PANEL_5V", "SEL_PANEL_12V",
474+
"SEL_BL_PWM", "SEL_BL_EN",
475+
"REVERSE_SCAN_PANEL", "GND_REV903";
476+
};
477+
478+
gpiowifi: io-expander@21 {
479+
compatible = "nxp,pca9554";
480+
reg = <0x21>;
481+
gpio-controller;
482+
#gpio-cells = <2>;
483+
gpio-line-names =
484+
"BL_LVDS_ENABLE_3V3", "BL_LVDS_PWM_3V3",
485+
"M2_BT_WAKE_3V3#", "M2_W_DISABLE2_3V3#",
486+
"TFT_PANEL_ENABLE_3V3", "TPM_RESET_3V3#",
487+
"CSI2_PD_3V3", "CSI2_RESET_3V3#";
488+
489+
/* BL_LVDS_PWM_3V3 is patch-wired to BL_PWM_3V3 on rev.903 */
490+
pwm-input-hog {
491+
gpio-hog;
492+
gpios = <1 0>;
493+
input;
494+
line-name = "BL_LVDS_PWM_3V3_HOG";
495+
};
496+
};
497+
498+
eepromlvds: eeprom@51 {
499+
compatible = "atmel,24c32";
500+
reg = <0x51>;
501+
pagesize = <32>;
502+
/* Optional EEPROM, disabled by default. */
503+
status = "disabled";
504+
};
411505
};
412506

413507
&i2c3 {
@@ -521,6 +615,7 @@
521615
pinctrl-0 = <&pinctrl_pcie0>;
522616
fsl,max-link-speed = <3>;
523617
reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
618+
vpcie-supply = <&reg_pcie0>;
524619
status = "okay";
525620
};
526621

@@ -598,7 +693,17 @@
598693
&uart4 {
599694
pinctrl-names = "default";
600695
pinctrl-0 = <&pinctrl_uart4>;
601-
status = "disabled";
696+
uart-has-rtscts;
697+
status = "okay";
698+
699+
bluetooth {
700+
compatible = "infineon,cyw55572-bt";
701+
brcm,requires-autobaud-mode;
702+
clocks = <&rtc 0>;
703+
clock-names = "txco";
704+
max-speed = <921600>;
705+
shutdown-gpios = <&gpiowifi 3 GPIO_ACTIVE_HIGH>;
706+
};
602707
};
603708

604709
&usb3_phy0 {
@@ -686,8 +791,6 @@
686791
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
687792
/* ENET_RST# */
688793
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6
689-
/* ENET_INT# */
690-
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090
691794
>;
692795
};
693796

@@ -709,8 +812,6 @@
709812
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
710813
/* ENET2_RST# */
711814
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6
712-
/* ENET2_INT# */
713-
MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090
714815
>;
715816
};
716817

@@ -754,10 +855,6 @@
754855

755856
/* PG_V_IN_VAR# */
756857
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000
757-
/* CSI2_PD_1V8 */
758-
MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0
759-
/* CSI2_RESET_1V8# */
760-
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0
761858

762859
/* DIS_USB_DN1 */
763860
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0
@@ -771,8 +868,14 @@
771868
/* GRAPHICS_PRSNT_1V8# */
772869
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000
773870

871+
/* TOUCH_RESET_3V3# */
872+
MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2
873+
/* TOUCH_INT# */
874+
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000140
774875
/* CLK_CCM_CLKO1_3V3 */
775876
MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10
877+
/* ENET_INT# (rev.900,901) or M2_WDIS_BTIRQ_3V3# (rev.903) */
878+
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000092
776879
>;
777880
};
778881

@@ -875,12 +978,10 @@
875978
fsl,pins = <
876979
/* M2_PCIE_RST# */
877980
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
878-
/* M2_W_DISABLE1_1V8# */
981+
/* M2_PCIE_WAKE_1V8# */
879982
MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2
880-
/* M2_W_DISABLE2_1V8# */
881-
MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2
882-
/* CLK_M2_32K768 */
883-
MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14
983+
/* M2_UART_WAKE_1V8# */
984+
MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000002
884985
/* M2_PCIE_WAKE# */
885986
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140
886987
/* M2_PCIE_CLKREQ# */
@@ -974,6 +1075,8 @@
9741075
fsl,pins = <
9751076
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
9761077
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
1078+
MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x149
1079+
MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x149
9771080
>;
9781081
};
9791082

@@ -1100,4 +1203,11 @@
11001203
MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26
11011204
>;
11021205
};
1206+
1207+
pinctrl_wifi: wifi-grp {
1208+
fsl,pins = <
1209+
/* WIFI_BT_RST_3V3# */
1210+
MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090
1211+
>;
1212+
};
11031213
};

0 commit comments

Comments
 (0)