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robherringwilldeacon
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perf: arm_spe: Use new PMSIDR_EL1 register enums
Now that the SPE register definitions include enums for some PMSIDR_EL1 fields, use them in the driver in place of magic values. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20220825-arm-spe-v8-7-v4-5-327f860daf28@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
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Lines changed: 10 additions & 10 deletions

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drivers/perf/arm_spe_pmu.c

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1006,32 +1006,32 @@ static void __arm_spe_pmu_dev_probe(void *info)
10061006
/* This field has a spaced out encoding, so just use a look-up */
10071007
fld = FIELD_GET(PMSIDR_EL1_INTERVAL, reg);
10081008
switch (fld) {
1009-
case 0:
1009+
case PMSIDR_EL1_INTERVAL_256:
10101010
spe_pmu->min_period = 256;
10111011
break;
1012-
case 2:
1012+
case PMSIDR_EL1_INTERVAL_512:
10131013
spe_pmu->min_period = 512;
10141014
break;
1015-
case 3:
1015+
case PMSIDR_EL1_INTERVAL_768:
10161016
spe_pmu->min_period = 768;
10171017
break;
1018-
case 4:
1018+
case PMSIDR_EL1_INTERVAL_1024:
10191019
spe_pmu->min_period = 1024;
10201020
break;
1021-
case 5:
1021+
case PMSIDR_EL1_INTERVAL_1536:
10221022
spe_pmu->min_period = 1536;
10231023
break;
1024-
case 6:
1024+
case PMSIDR_EL1_INTERVAL_2048:
10251025
spe_pmu->min_period = 2048;
10261026
break;
1027-
case 7:
1027+
case PMSIDR_EL1_INTERVAL_3072:
10281028
spe_pmu->min_period = 3072;
10291029
break;
10301030
default:
10311031
dev_warn(dev, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n",
10321032
fld);
10331033
fallthrough;
1034-
case 8:
1034+
case PMSIDR_EL1_INTERVAL_4096:
10351035
spe_pmu->min_period = 4096;
10361036
}
10371037

@@ -1050,10 +1050,10 @@ static void __arm_spe_pmu_dev_probe(void *info)
10501050
dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n",
10511051
fld);
10521052
fallthrough;
1053-
case 2:
1053+
case PMSIDR_EL1_COUNTSIZE_12_BIT_SAT:
10541054
spe_pmu->counter_sz = 12;
10551055
break;
1056-
case 3:
1056+
case PMSIDR_EL1_COUNTSIZE_16_BIT_SAT:
10571057
spe_pmu->counter_sz = 16;
10581058
}
10591059

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