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robherring
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perf: arm_spe: Drop BIT() and use FIELD_GET/PREP accessors
Now that generated sysregs are in place, update the register field accesses. The use of BIT() is no longer needed with the new defines. Use FIELD_GET and FIELD_PREP instead of open coding masking and shifting. No functional change. Tested-by: James Clark <james.clark@arm.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> Link: https://lore.kernel.org/r/20220825-arm-spe-v8-7-v4-4-327f860daf28@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
1 parent 9569360 commit 2d347ac

1 file changed

Lines changed: 34 additions & 36 deletions

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‎drivers/perf/arm_spe_pmu.c‎

Lines changed: 34 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -283,18 +283,18 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event)
283283
struct perf_event_attr *attr = &event->attr;
284284
u64 reg = 0;
285285

286-
reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << PMSCR_EL1_TS_SHIFT;
287-
reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << PMSCR_EL1_PA_SHIFT;
288-
reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << PMSCR_EL1_PCT_SHIFT;
286+
reg |= FIELD_PREP(PMSCR_EL1_TS, ATTR_CFG_GET_FLD(attr, ts_enable));
287+
reg |= FIELD_PREP(PMSCR_EL1_PA, ATTR_CFG_GET_FLD(attr, pa_enable));
288+
reg |= FIELD_PREP(PMSCR_EL1_PCT, ATTR_CFG_GET_FLD(attr, pct_enable));
289289

290290
if (!attr->exclude_user)
291-
reg |= BIT(PMSCR_EL1_E0SPE_SHIFT);
291+
reg |= PMSCR_EL1_E0SPE;
292292

293293
if (!attr->exclude_kernel)
294-
reg |= BIT(PMSCR_EL1_E1SPE_SHIFT);
294+
reg |= PMSCR_EL1_E1SPE;
295295

296296
if (get_spe_event_has_cx(event))
297-
reg |= BIT(PMSCR_EL1_CX_SHIFT);
297+
reg |= PMSCR_EL1_CX;
298298

299299
return reg;
300300
}
@@ -322,7 +322,7 @@ static u64 arm_spe_event_to_pmsirr(struct perf_event *event)
322322

323323
arm_spe_event_sanitise_period(event);
324324

325-
reg |= ATTR_CFG_GET_FLD(attr, jitter) << PMSIRR_EL1_RND_SHIFT;
325+
reg |= FIELD_PREP(PMSIRR_EL1_RND, ATTR_CFG_GET_FLD(attr, jitter));
326326
reg |= event->hw.sample_period;
327327

328328
return reg;
@@ -333,18 +333,18 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *event)
333333
struct perf_event_attr *attr = &event->attr;
334334
u64 reg = 0;
335335

336-
reg |= ATTR_CFG_GET_FLD(attr, load_filter) << PMSFCR_EL1_LD_SHIFT;
337-
reg |= ATTR_CFG_GET_FLD(attr, store_filter) << PMSFCR_EL1_ST_SHIFT;
338-
reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << PMSFCR_EL1_B_SHIFT;
336+
reg |= FIELD_PREP(PMSFCR_EL1_LD, ATTR_CFG_GET_FLD(attr, load_filter));
337+
reg |= FIELD_PREP(PMSFCR_EL1_ST, ATTR_CFG_GET_FLD(attr, store_filter));
338+
reg |= FIELD_PREP(PMSFCR_EL1_B, ATTR_CFG_GET_FLD(attr, branch_filter));
339339

340340
if (reg)
341-
reg |= BIT(PMSFCR_EL1_FT_SHIFT);
341+
reg |= PMSFCR_EL1_FT;
342342

343343
if (ATTR_CFG_GET_FLD(attr, event_filter))
344-
reg |= BIT(PMSFCR_EL1_FE_SHIFT);
344+
reg |= PMSFCR_EL1_FE;
345345

346346
if (ATTR_CFG_GET_FLD(attr, min_latency))
347-
reg |= BIT(PMSFCR_EL1_FL_SHIFT);
347+
reg |= PMSFCR_EL1_FL;
348348

349349
return reg;
350350
}
@@ -358,8 +358,7 @@ static u64 arm_spe_event_to_pmsevfr(struct perf_event *event)
358358
static u64 arm_spe_event_to_pmslatfr(struct perf_event *event)
359359
{
360360
struct perf_event_attr *attr = &event->attr;
361-
return ATTR_CFG_GET_FLD(attr, min_latency)
362-
<< PMSLATFR_EL1_MINLAT_SHIFT;
361+
return FIELD_PREP(PMSLATFR_EL1_MINLAT, ATTR_CFG_GET_FLD(attr, min_latency));
363362
}
364363

365364
static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len)
@@ -511,7 +510,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle,
511510
limit = buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle)
512511
: arm_spe_pmu_next_off(handle);
513512
if (limit)
514-
limit |= BIT(PMBLIMITR_EL1_E_SHIFT);
513+
limit |= PMBLIMITR_EL1_E;
515514

516515
limit += (u64)buf->base;
517516
base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf);
@@ -570,23 +569,23 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle)
570569

571570
/* Service required? */
572571
pmbsr = read_sysreg_s(SYS_PMBSR_EL1);
573-
if (!(pmbsr & BIT(PMBSR_EL1_S_SHIFT)))
572+
if (!FIELD_GET(PMBSR_EL1_S, pmbsr))
574573
return SPE_PMU_BUF_FAULT_ACT_SPURIOUS;
575574

576575
/*
577576
* If we've lost data, disable profiling and also set the PARTIAL
578577
* flag to indicate that the last record is corrupted.
579578
*/
580-
if (pmbsr & BIT(PMBSR_EL1_DL_SHIFT))
579+
if (FIELD_GET(PMBSR_EL1_DL, pmbsr))
581580
perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED |
582581
PERF_AUX_FLAG_PARTIAL);
583582

584583
/* Report collisions to userspace so that it can up the period */
585-
if (pmbsr & BIT(PMBSR_EL1_COLL_SHIFT))
584+
if (FIELD_GET(PMBSR_EL1_COLL, pmbsr))
586585
perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION);
587586

588587
/* We only expect buffer management events */
589-
switch (FIELD_GET(PMBSR_EL1_EC_MASK, pmbsr)) {
588+
switch (FIELD_GET(PMBSR_EL1_EC, pmbsr)) {
590589
case PMBSR_EL1_EC_BUF:
591590
/* Handled below */
592591
break;
@@ -716,23 +715,22 @@ static int arm_spe_pmu_event_init(struct perf_event *event)
716715
return -EINVAL;
717716

718717
reg = arm_spe_event_to_pmsfcr(event);
719-
if ((reg & BIT(PMSFCR_EL1_FE_SHIFT)) &&
718+
if ((FIELD_GET(PMSFCR_EL1_FE, reg)) &&
720719
!(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT))
721720
return -EOPNOTSUPP;
722721

723-
if ((reg & BIT(PMSFCR_EL1_FT_SHIFT)) &&
722+
if ((FIELD_GET(PMSFCR_EL1_FT, reg)) &&
724723
!(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP))
725724
return -EOPNOTSUPP;
726725

727-
if ((reg & BIT(PMSFCR_EL1_FL_SHIFT)) &&
726+
if ((FIELD_GET(PMSFCR_EL1_FL, reg)) &&
728727
!(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT))
729728
return -EOPNOTSUPP;
730729

731730
set_spe_event_has_cx(event);
732731
reg = arm_spe_event_to_pmscr(event);
733732
if (!perfmon_capable() &&
734-
(reg & (BIT(PMSCR_EL1_PA_SHIFT) |
735-
BIT(PMSCR_EL1_PCT_SHIFT))))
733+
(reg & (PMSCR_EL1_PA | PMSCR_EL1_PCT)))
736734
return -EACCES;
737735

738736
return 0;
@@ -970,14 +968,14 @@ static void __arm_spe_pmu_dev_probe(void *info)
970968

971969
/* Read PMBIDR first to determine whether or not we have access */
972970
reg = read_sysreg_s(SYS_PMBIDR_EL1);
973-
if (reg & BIT(PMBIDR_EL1_P_SHIFT)) {
971+
if (FIELD_GET(PMBIDR_EL1_P, reg)) {
974972
dev_err(dev,
975973
"profiling buffer owned by higher exception level\n");
976974
return;
977975
}
978976

979977
/* Minimum alignment. If it's out-of-range, then fail the probe */
980-
fld = (reg & PMBIDR_EL1_ALIGN_MASK) >> PMBIDR_EL1_ALIGN_SHIFT;
978+
fld = FIELD_GET(PMBIDR_EL1_ALIGN, reg);
981979
spe_pmu->align = 1 << fld;
982980
if (spe_pmu->align > SZ_2K) {
983981
dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n",
@@ -987,26 +985,26 @@ static void __arm_spe_pmu_dev_probe(void *info)
987985

988986
/* It's now safe to read PMSIDR and figure out what we've got */
989987
reg = read_sysreg_s(SYS_PMSIDR_EL1);
990-
if (reg & BIT(PMSIDR_EL1_FE_SHIFT))
988+
if (FIELD_GET(PMSIDR_EL1_FE, reg))
991989
spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT;
992990

993-
if (reg & BIT(PMSIDR_EL1_FT_SHIFT))
991+
if (FIELD_GET(PMSIDR_EL1_FT, reg))
994992
spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP;
995993

996-
if (reg & BIT(PMSIDR_EL1_FL_SHIFT))
994+
if (FIELD_GET(PMSIDR_EL1_FL, reg))
997995
spe_pmu->features |= SPE_PMU_FEAT_FILT_LAT;
998996

999-
if (reg & BIT(PMSIDR_EL1_ARCHINST_SHIFT))
997+
if (FIELD_GET(PMSIDR_EL1_ARCHINST, reg))
1000998
spe_pmu->features |= SPE_PMU_FEAT_ARCH_INST;
1001999

1002-
if (reg & BIT(PMSIDR_EL1_LDS_SHIFT))
1000+
if (FIELD_GET(PMSIDR_EL1_LDS, reg))
10031001
spe_pmu->features |= SPE_PMU_FEAT_LDS;
10041002

1005-
if (reg & BIT(PMSIDR_EL1_ERND_SHIFT))
1003+
if (FIELD_GET(PMSIDR_EL1_ERND, reg))
10061004
spe_pmu->features |= SPE_PMU_FEAT_ERND;
10071005

10081006
/* This field has a spaced out encoding, so just use a look-up */
1009-
fld = (reg & PMSIDR_EL1_INTERVAL_MASK) >> PMSIDR_EL1_INTERVAL_SHIFT;
1007+
fld = FIELD_GET(PMSIDR_EL1_INTERVAL, reg);
10101008
switch (fld) {
10111009
case 0:
10121010
spe_pmu->min_period = 256;
@@ -1038,15 +1036,15 @@ static void __arm_spe_pmu_dev_probe(void *info)
10381036
}
10391037

10401038
/* Maximum record size. If it's out-of-range, then fail the probe */
1041-
fld = (reg & PMSIDR_EL1_MAXSIZE_MASK) >> PMSIDR_EL1_MAXSIZE_SHIFT;
1039+
fld = FIELD_GET(PMSIDR_EL1_MAXSIZE, reg);
10421040
spe_pmu->max_record_sz = 1 << fld;
10431041
if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) {
10441042
dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n",
10451043
fld, smp_processor_id());
10461044
return;
10471045
}
10481046

1049-
fld = (reg & PMSIDR_EL1_COUNTSIZE_MASK) >> PMSIDR_EL1_COUNTSIZE_SHIFT;
1047+
fld = FIELD_GET(PMSIDR_EL1_COUNTSIZE, reg);
10501048
switch (fld) {
10511049
default:
10521050
dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n",

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