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Merge tag 'renesas-clk-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the R-Car V4H and RZ/V2M SoCs - Add the Universal Flash Storage clock on R-Car S4-8 - Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on RZ/G2UL - Add display clock support on RZ/G2L - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (36 commits) clk: renesas: r9a09g011: Add eth clock and reset entries clk: renesas: Add RZ/V2M support using the rzg2l driver clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg clk: renesas: rzg2l: Make use of CLK_MON registers optional clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers clk: renesas: rzg2l: Add read only versions of the clk macros clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC clk: renesas: r9a07g044: Fix OSTM1 module clock name clk: renesas: r9a07g043: Add clock and reset entries for ADC clk: renesas: r9a07g043: Add TSU clock and reset entry clk: renesas: r9a07g043: Add RSPI clock and reset entries clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller clk: renesas: r9a07g044: Add DSI clock and reset entries clk: renesas: r9a07g044: Add LCDC clock and reset entries clk: renesas: r9a07g044: Add M4 Clock support clk: renesas: r9a07g044: Add M3 Clock support clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support clk: renesas: r9a07g044: Add M1 clock support clk: renesas: rzg2l: Add DSI divider clk support ...
2 parents 9f4f53e + 23426d1 commit 13982e8

20 files changed

Lines changed: 1644 additions & 73 deletions

‎Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,7 @@ properties:
4949
- renesas,r8a77995-cpg-mssr # R-Car D3
5050
- renesas,r8a779a0-cpg-mssr # R-Car V3U
5151
- renesas,r8a779f0-cpg-mssr # R-Car S4-8
52+
- renesas,r8a779g0-cpg-mssr # R-Car V4H
5253

5354
reg:
5455
maxItems: 1

‎Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,14 +4,15 @@
44
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
55
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
66

7-
title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
7+
title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
88

99
maintainers:
1010
- Geert Uytterhoeven <geert+renesas@glider.be>
1111

1212
description: |
1313
On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
14-
Standby Mode share the same register block.
14+
Standby Mode share the same register block. On RZ/V2M, the functionality is
15+
similar, but does not have Clock Monitor Registers.
1516
1617
They provide the following functionalities:
1718
- The CPG block generates various core clocks,
@@ -26,6 +27,7 @@ properties:
2627
- renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}
2728
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
2829
- renesas,r9a07g054-cpg # RZ/V2L
30+
- renesas,r9a09g011-cpg # RZ/V2M
2931

3032
reg:
3133
maxItems: 1
@@ -43,9 +45,10 @@ properties:
4345
description: |
4446
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
4547
and a core clock reference, as defined in
46-
<dt-bindings/clock/r9a07g*-cpg.h>
48+
<dt-bindings/clock/r9a0*-cpg.h>
4749
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
48-
a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
50+
a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
51+
<dt-bindings/clock/r9a09g011-cpg.h>.
4952
const: 2
5053

5154
'#power-domain-cells':
@@ -59,7 +62,7 @@ properties:
5962
'#reset-cells':
6063
description:
6164
The single reset specifier cell must be the module number, as defined in
62-
the <dt-bindings/clock/r9a07g0*-cpg.h>.
65+
the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
6366
const: 1
6467

6568
required:

‎drivers/clk/renesas/Kconfig‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,10 +32,12 @@ config CLK_RENESAS
3232
select CLK_R8A77995 if ARCH_R8A77995
3333
select CLK_R8A779A0 if ARCH_R8A779A0
3434
select CLK_R8A779F0 if ARCH_R8A779F0
35+
select CLK_R8A779G0 if ARCH_R8A779G0
3536
select CLK_R9A06G032 if ARCH_R9A06G032
3637
select CLK_R9A07G043 if ARCH_R9A07G043
3738
select CLK_R9A07G044 if ARCH_R9A07G044
3839
select CLK_R9A07G054 if ARCH_R9A07G054
40+
select CLK_R9A09G011 if ARCH_R9A09G011
3941
select CLK_SH73A0 if ARCH_SH73A0
4042

4143
if CLK_RENESAS
@@ -158,6 +160,10 @@ config CLK_R8A779F0
158160
bool "R-Car S4-8 clock support" if COMPILE_TEST
159161
select CLK_RCAR_GEN4_CPG
160162

163+
config CLK_R8A779G0
164+
bool "R-Car V4H clock support" if COMPILE_TEST
165+
select CLK_RCAR_GEN4_CPG
166+
161167
config CLK_R9A06G032
162168
bool "RZ/N1D clock support" if COMPILE_TEST
163169

@@ -173,6 +179,10 @@ config CLK_R9A07G054
173179
bool "RZ/V2L clock support" if COMPILE_TEST
174180
select CLK_RZG2L
175181

182+
config CLK_R9A09G011
183+
bool "RZ/V2M clock support" if COMPILE_TEST
184+
select CLK_RZG2L
185+
176186
config CLK_SH73A0
177187
bool "SH-Mobile AG5 clock support" if COMPILE_TEST
178188
select CLK_RENESAS_CPG_MSTP

‎drivers/clk/renesas/Makefile‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,10 +29,12 @@ obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
2929
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
3030
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
3131
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
32+
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
3233
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
3334
obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
3435
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
3536
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
37+
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
3638
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
3739

3840
# Family

‎drivers/clk/renesas/r8a779a0-cpg-mssr.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
244244
/*
245245
* MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
246246
* 14 13 (MHz) 21 31
247-
* --------------------------------------------------------
247+
* ----------------------------------------------------------------
248248
* 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16
249249
* 0 1 20 x 1 x106 x180 x106 x120 x160 /19
250250
* 1 0 Prohibited setting
@@ -253,11 +253,11 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {
253253
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
254254
(((md) & BIT(13)) >> 13))
255255
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
256-
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
257-
{ 1, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 16, },
258-
{ 1, 106, 1, 0, 0, 0, 0, 160, 1, 0, 0, 19, },
259-
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
260-
{ 2, 128, 1, 0, 0, 0, 0, 192, 1, 0, 0, 32, },
256+
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
257+
{ 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, },
258+
{ 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, },
259+
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
260+
{ 2, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 32, },
261261
};
262262

263263

‎drivers/clk/renesas/r8a779f0-cpg-mssr.c‎

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -132,6 +132,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
132132
DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
133133
DEF_MOD("wdt", 907, R8A779F0_CLK_R),
134134
DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M),
135+
DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC),
135136
};
136137

137138
static const unsigned int r8a779f0_crit_mod_clks[] __initconst = {
@@ -142,23 +143,23 @@ static const unsigned int r8a779f0_crit_mod_clks[] __initconst = {
142143
* CPG Clock Data
143144
*/
144145
/*
145-
* MD EXTAL PLL1 PLL2 PLL3 PLL5 PLL6 OSC
146+
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
146147
* 14 13 (MHz)
147-
* ----------------------------------------------------------------
148-
* 0 0 16 / 1 x200 x150 x200 x200 x134 /15
149-
* 0 1 20 / 1 x160 x120 x160 x160 x106 /19
148+
* ------------------------------------------------------------------------
149+
* 0 0 16 / 1 x200 x150 x200 n/a x200 x134 /15
150+
* 0 1 20 / 1 x160 x120 x160 n/a x160 x106 /19
150151
* 1 0 Prohibited setting
151-
* 1 1 40 / 2 x160 x120 x160 x160 x106 /38
152+
* 1 1 40 / 2 x160 x120 x160 n/a x160 x106 /38
152153
*/
153154
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
154155
(((md) & BIT(13)) >> 13))
155156

156157
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
157-
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
158-
{ 1, 200, 1, 150, 1, 200, 1, 200, 1, 134, 1, 15, },
159-
{ 1, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 19, },
160-
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
161-
{ 2, 160, 1, 120, 1, 160, 1, 160, 1, 106, 1, 38, },
158+
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
159+
{ 1, 200, 1, 150, 1, 200, 1, 0, 0, 200, 1, 134, 1, 15, },
160+
{ 1, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 19, },
161+
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
162+
{ 2, 160, 1, 120, 1, 160, 1, 0, 0, 160, 1, 106, 1, 38, },
162163
};
163164

164165
static int __init r8a779f0_cpg_mssr_init(struct device *dev)

‎drivers/clk/renesas/r8a779g0-cpg-mssr.c‎

Lines changed: 218 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,218 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* r8a779g0 Clock Pulse Generator / Module Standby and Software Reset
4+
*
5+
* Copyright (C) 2022 Renesas Electronics Corp.
6+
*
7+
* Based on r8a779f0-cpg-mssr.c
8+
*/
9+
10+
#include <linux/bitfield.h>
11+
#include <linux/clk.h>
12+
#include <linux/clk-provider.h>
13+
#include <linux/device.h>
14+
#include <linux/err.h>
15+
#include <linux/kernel.h>
16+
#include <linux/soc/renesas/rcar-rst.h>
17+
18+
#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
19+
20+
#include "renesas-cpg-mssr.h"
21+
#include "rcar-gen4-cpg.h"
22+
23+
enum clk_ids {
24+
/* Core Clock Outputs exported to DT */
25+
LAST_DT_CORE_CLK = R8A779G0_CLK_R,
26+
27+
/* External Input Clocks */
28+
CLK_EXTAL,
29+
CLK_EXTALR,
30+
31+
/* Internal Core Clocks */
32+
CLK_MAIN,
33+
CLK_PLL1,
34+
CLK_PLL2,
35+
CLK_PLL3,
36+
CLK_PLL4,
37+
CLK_PLL5,
38+
CLK_PLL6,
39+
CLK_PLL1_DIV2,
40+
CLK_PLL2_DIV2,
41+
CLK_PLL3_DIV2,
42+
CLK_PLL4_DIV2,
43+
CLK_PLL5_DIV2,
44+
CLK_PLL5_DIV4,
45+
CLK_PLL6_DIV2,
46+
CLK_S0,
47+
CLK_S0_VIO,
48+
CLK_S0_VC,
49+
CLK_S0_HSC,
50+
CLK_SV_VIP,
51+
CLK_SV_IR,
52+
CLK_SDSRC,
53+
CLK_RPCSRC,
54+
CLK_VIO,
55+
CLK_VC,
56+
CLK_OCO,
57+
58+
/* Module Clocks */
59+
MOD_CLK_BASE
60+
};
61+
62+
static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
63+
/* External Clock Inputs */
64+
DEF_INPUT("extal", CLK_EXTAL),
65+
DEF_INPUT("extalr", CLK_EXTALR),
66+
67+
/* Internal Core Clocks */
68+
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
69+
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
70+
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
71+
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
72+
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
73+
DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
74+
DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
75+
76+
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
77+
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
78+
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1),
79+
DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1),
80+
DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
81+
DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
82+
DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 2, 1),
83+
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
84+
DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1),
85+
DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1),
86+
DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1),
87+
DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1),
88+
DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1),
89+
DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
90+
DEF_RATE(".oco", CLK_OCO, 32768),
91+
92+
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
93+
DEF_FIXED(".vio", CLK_VIO, CLK_PLL5_DIV2, 3, 1),
94+
DEF_FIXED(".vc", CLK_VC, CLK_PLL5_DIV2, 3, 1),
95+
96+
/* Core Clock Outputs */
97+
DEF_FIXED("s0d2", R8A779G0_CLK_S0D2, CLK_S0, 2, 1),
98+
DEF_FIXED("s0d3", R8A779G0_CLK_S0D3, CLK_S0, 3, 1),
99+
DEF_FIXED("s0d4", R8A779G0_CLK_S0D4, CLK_S0, 4, 1),
100+
DEF_FIXED("cl16m", R8A779G0_CLK_CL16M, CLK_S0, 48, 1),
101+
DEF_FIXED("s0d1_vio", R8A779G0_CLK_S0D1_VIO, CLK_S0_VIO, 1, 1),
102+
DEF_FIXED("s0d2_vio", R8A779G0_CLK_S0D2_VIO, CLK_S0_VIO, 2, 1),
103+
DEF_FIXED("s0d4_vio", R8A779G0_CLK_S0D4_VIO, CLK_S0_VIO, 4, 1),
104+
DEF_FIXED("s0d8_vio", R8A779G0_CLK_S0D8_VIO, CLK_S0_VIO, 8, 1),
105+
DEF_FIXED("s0d1_vc", R8A779G0_CLK_S0D1_VC, CLK_S0_VC, 1, 1),
106+
DEF_FIXED("s0d2_vc", R8A779G0_CLK_S0D2_VC, CLK_S0_VC, 2, 1),
107+
DEF_FIXED("s0d4_vc", R8A779G0_CLK_S0D4_VC, CLK_S0_VC, 4, 1),
108+
DEF_FIXED("s0d2_mm", R8A779G0_CLK_S0D2_MM, CLK_S0, 2, 1),
109+
DEF_FIXED("s0d4_mm", R8A779G0_CLK_S0D4_MM, CLK_S0, 4, 1),
110+
DEF_FIXED("cl16m_mm", R8A779G0_CLK_CL16M_MM, CLK_S0, 48, 1),
111+
DEF_FIXED("s0d2_u3dg", R8A779G0_CLK_S0D2_U3DG, CLK_S0, 2, 1),
112+
DEF_FIXED("s0d4_u3dg", R8A779G0_CLK_S0D4_U3DG, CLK_S0, 4, 1),
113+
DEF_FIXED("s0d2_rt", R8A779G0_CLK_S0D2_RT, CLK_S0, 2, 1),
114+
DEF_FIXED("s0d3_rt", R8A779G0_CLK_S0D3_RT, CLK_S0, 3, 1),
115+
DEF_FIXED("s0d4_rt", R8A779G0_CLK_S0D4_RT, CLK_S0, 4, 1),
116+
DEF_FIXED("s0d6_rt", R8A779G0_CLK_S0D6_RT, CLK_S0, 6, 1),
117+
DEF_FIXED("s0d24_rt", R8A779G0_CLK_S0D24_RT, CLK_S0, 24, 1),
118+
DEF_FIXED("cl16m_rt", R8A779G0_CLK_CL16M_RT, CLK_S0, 48, 1),
119+
DEF_FIXED("s0d2_per", R8A779G0_CLK_S0D2_PER, CLK_S0, 2, 1),
120+
DEF_FIXED("s0d3_per", R8A779G0_CLK_S0D3_PER, CLK_S0, 3, 1),
121+
DEF_FIXED("s0d4_per", R8A779G0_CLK_S0D4_PER, CLK_S0, 4, 1),
122+
DEF_FIXED("s0d6_per", R8A779G0_CLK_S0D6_PER, CLK_S0, 6, 1),
123+
DEF_FIXED("s0d12_per", R8A779G0_CLK_S0D12_PER, CLK_S0, 12, 1),
124+
DEF_FIXED("s0d24_per", R8A779G0_CLK_S0D24_PER, CLK_S0, 24, 1),
125+
DEF_FIXED("cl16m_per", R8A779G0_CLK_CL16M_PER, CLK_S0, 48, 1),
126+
DEF_FIXED("s0d1_hsc", R8A779G0_CLK_S0D1_HSC, CLK_S0_HSC, 1, 1),
127+
DEF_FIXED("s0d2_hsc", R8A779G0_CLK_S0D2_HSC, CLK_S0_HSC, 2, 1),
128+
DEF_FIXED("s0d4_hsc", R8A779G0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
129+
DEF_FIXED("cl16m_hsc", R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
130+
DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
131+
DEF_FIXED("svd1_ir", R8A779G0_CLK_SVD1_IR, CLK_SV_IR, 1, 1),
132+
DEF_FIXED("svd2_ir", R8A779G0_CLK_SVD2_IR, CLK_SV_IR, 2, 1),
133+
DEF_FIXED("svd1_vip", R8A779G0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1),
134+
DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
135+
DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
136+
DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
137+
DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
138+
DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
139+
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
140+
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
141+
142+
DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, CLK_SDSRC, 0x870),
143+
DEF_DIV6P1("mso", R8A779G0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
144+
145+
DEF_BASE("rpc", R8A779G0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
146+
DEF_BASE("rpcd2", R8A779G0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, R8A779G0_CLK_RPC),
147+
148+
DEF_GEN4_OSC("osc", R8A779G0_CLK_OSC, CLK_EXTAL, 8),
149+
DEF_GEN4_MDSEL("r", R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
150+
};
151+
152+
static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
153+
DEF_MOD("hscif0", 514, R8A779G0_CLK_S0D3_PER),
154+
DEF_MOD("hscif1", 515, R8A779G0_CLK_S0D3_PER),
155+
DEF_MOD("hscif2", 516, R8A779G0_CLK_S0D3_PER),
156+
DEF_MOD("hscif3", 517, R8A779G0_CLK_S0D3_PER),
157+
};
158+
159+
/*
160+
* CPG Clock Data
161+
*/
162+
/*
163+
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
164+
* 14 13 (MHz)
165+
* ------------------------------------------------------------------------
166+
* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /15
167+
* 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
168+
* 1 0 Prohibited setting
169+
* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /38
170+
*/
171+
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
172+
(((md) & BIT(13)) >> 13))
173+
174+
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
175+
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
176+
{ 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 15, },
177+
{ 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1, 19, },
178+
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
179+
{ 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 38, },
180+
};
181+
182+
static int __init r8a779g0_cpg_mssr_init(struct device *dev)
183+
{
184+
const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
185+
u32 cpg_mode;
186+
int error;
187+
188+
error = rcar_rst_read_mode_pins(&cpg_mode);
189+
if (error)
190+
return error;
191+
192+
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
193+
if (!cpg_pll_config->extal_div) {
194+
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
195+
return -EINVAL;
196+
}
197+
198+
return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
199+
}
200+
201+
const struct cpg_mssr_info r8a779g0_cpg_mssr_info __initconst = {
202+
/* Core Clocks */
203+
.core_clks = r8a779g0_core_clks,
204+
.num_core_clks = ARRAY_SIZE(r8a779g0_core_clks),
205+
.last_dt_core_clk = LAST_DT_CORE_CLK,
206+
.num_total_core_clks = MOD_CLK_BASE,
207+
208+
/* Module Clocks */
209+
.mod_clks = r8a779g0_mod_clks,
210+
.num_mod_clks = ARRAY_SIZE(r8a779g0_mod_clks),
211+
.num_hw_mod_clks = 30 * 32,
212+
213+
/* Callbacks */
214+
.init = r8a779g0_cpg_mssr_init,
215+
.cpg_clk_register = rcar_gen4_cpg_clk_register,
216+
217+
.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
218+
};

‎drivers/clk/renesas/r9a06g032-clocks.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -256,7 +256,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
256256
D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302),
257257
D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2),
258258
D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0),
259-
D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0, 0, 0, 0, 0, 0),
259+
D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0xa03, 0, 0xa02, 0, 0, 0),
260260
D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82),
261261
D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662),
262262
D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0),

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