Skip to content

Commit 13c916a

Browse files
torvaldstorvalds
committed
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "Not much changed in the clk framework this time except the clk.h consumer API moved the context saving APIs around to fix a build error in certain configurations. There was a change to the core framework for CLK_OPS_PARENT_ENABLE behavior during registration, but it wrecked existing drivers that didn't expect things to be turned off during clk registration so it got reverted. This cycle is really a large collection of new clk drivers, primarily for Qualcomm SoCs but also for Amlogic, SpacemiT, Google, and Aspeed. Another big change in here is support for automatic hardware clock gating on Samsung SoCs where the clks turn on and off when needed. Ideally more vendors move to this method for better power savings. The highlights are in the updates section below. Beyond all the new drivers we have a bunch of cleanups like converting drivers from divider_round_rate() to divider_determine_rate() and using scoped for each OF child loops. Otherwise it's the usual data fixes and plugging reference leaks, etc. that's all pretty ordinary but not critical enough to fix until the next release. New Drivers: - Qualcomm Kaanapali global, tcsr, rpmh, display, gpu, camera, and video clk controllers - Qualcomm SM8750 camera clk controllers - Qualcomm MSM8940 and SDM439 global clk controllers - Google GS101 Display Process Unit (DPU) clk controllers - SpacemiT K3 clk controllers - Amlogic t7 clk controllers - Aspeed AST2700 clk controllers Updates: - Convert clock dividers from round_rate() to determine_rate() - Fix sparse warnings, kernel-doc warnings, and plug leaked OF refs - Automatic hardware clk gating on Google GS101 SoCs - Amlogic s4 video clks - CAN-FD clks and resets on Renesas RZ/T2H, RZ/N2H, RZ/V2H, and RZ/V2N - Expanded Serial Peripheral Interface (xSPI) clocks and resets on Renesas RZ/T21H and RZ/N2H - DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and resets on Renesas RZ/V2N - More serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N - CPU frequency scaling on T-HEAD TH1520" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (165 commits) clk: aspeed: Add reset for HACE/VIDEO dt-bindings: clock: aspeed: Add VIDEO reset definition clk: aspeed: add AST2700 clock driver MAINTAINERS: Add entry for ASPEED clock drivers. clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory. Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc" clk: Disable KUNIT_UML_PCI dt-bindings: clk: rs9: Fix DIF pattern match clk: rs9: Convert to DEFINE_SIMPLE_DEV_PM_OPS() clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841 clk: qcom: sm8750: Constify 'qcom_cc_desc' in SM8750 camcc clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc clk: zynqmp: divider: Fix zynqmp_clk_divider_determine_rate kerneldoc clk: mediatek: Fix error handling in runtime PM setup clk: mediatek: don't select clk-mt8192 for all ARM64 builds clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks clk: mediatek: Refactor pllfh registration to pass device clk: mediatek: Pass device to clk_hw_register for PLLs clk: mediatek: Refactor pll registration to pass device clk: Respect CLK_OPS_PARENT_ENABLE during recalc ...
2 parents ca4ee40 + 5921ae2 commit 13c916a

189 files changed

Lines changed: 23417 additions & 943 deletions

File tree

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml‎

Lines changed: 116 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,116 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
3+
%YAML 1.2
4+
---
5+
$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml#
6+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7+
8+
title: Amlogic T7 Peripherals Clock Controller
9+
10+
maintainers:
11+
- Neil Armstrong <neil.armstrong@linaro.org>
12+
- Jerome Brunet <jbrunet@baylibre.com>
13+
- Xianwei Zhao <xianwei.zhao@amlogic.com>
14+
- Jian Hu <jian.hu@amlogic.com>
15+
16+
properties:
17+
compatible:
18+
const: amlogic,t7-peripherals-clkc
19+
20+
reg:
21+
maxItems: 1
22+
23+
'#clock-cells':
24+
const: 1
25+
26+
clocks:
27+
minItems: 14
28+
items:
29+
- description: input oscillator
30+
- description: input sys clk
31+
- description: input fixed pll
32+
- description: input fclk div 2
33+
- description: input fclk div 2p5
34+
- description: input fclk div 3
35+
- description: input fclk div 4
36+
- description: input fclk div 5
37+
- description: input fclk div 7
38+
- description: input hifi pll
39+
- description: input gp0 pll
40+
- description: input gp1 pll
41+
- description: input mpll1
42+
- description: input mpll2
43+
- description: external input rmii oscillator (optional)
44+
- description: input video pll0 (optional)
45+
- description: external pad input for rtc (optional)
46+
47+
clock-names:
48+
minItems: 14
49+
items:
50+
- const: xtal
51+
- const: sys
52+
- const: fix
53+
- const: fdiv2
54+
- const: fdiv2p5
55+
- const: fdiv3
56+
- const: fdiv4
57+
- const: fdiv5
58+
- const: fdiv7
59+
- const: hifi
60+
- const: gp0
61+
- const: gp1
62+
- const: mpll1
63+
- const: mpll2
64+
- const: ext_rmii
65+
- const: vid_pll0
66+
- const: ext_rtc
67+
68+
required:
69+
- compatible
70+
- '#clock-cells'
71+
- reg
72+
- clocks
73+
- clock-names
74+
75+
additionalProperties: false
76+
77+
examples:
78+
- |
79+
apb {
80+
#address-cells = <2>;
81+
#size-cells = <2>;
82+
83+
clkc_periphs:clock-controller@0 {
84+
compatible = "amlogic,t7-peripherals-clkc";
85+
reg = <0 0x0 0 0x1c8>;
86+
#clock-cells = <1>;
87+
clocks = <&xtal>,
88+
<&scmi_clk 13>,
89+
<&scmi_clk 16>,
90+
<&scmi_clk 18>,
91+
<&scmi_clk 20>,
92+
<&scmi_clk 22>,
93+
<&scmi_clk 24>,
94+
<&scmi_clk 26>,
95+
<&scmi_clk 28>,
96+
<&hifi 1>,
97+
<&gp0 1>,
98+
<&gp1 1>,
99+
<&mpll 4>,
100+
<&mpll 6>;
101+
clock-names = "xtal",
102+
"sys",
103+
"fix",
104+
"fdiv2",
105+
"fdiv2p5",
106+
"fdiv3",
107+
"fdiv4",
108+
"fdiv5",
109+
"fdiv7",
110+
"hifi",
111+
"gp0",
112+
"gp1",
113+
"mpll1",
114+
"mpll2";
115+
};
116+
};

‎Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml‎

Lines changed: 114 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,114 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
3+
%YAML 1.2
4+
---
5+
$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
6+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7+
8+
title: Amlogic T7 PLL Clock Control Controller
9+
10+
maintainers:
11+
- Neil Armstrong <neil.armstrong@linaro.org>
12+
- Jerome Brunet <jbrunet@baylibre.com>
13+
- Jian Hu <jian.hu@amlogic.com>
14+
- Xianwei Zhao <xianwei.zhao@amlogic.com>
15+
16+
properties:
17+
compatible:
18+
enum:
19+
- amlogic,t7-gp0-pll
20+
- amlogic,t7-gp1-pll
21+
- amlogic,t7-hifi-pll
22+
- amlogic,t7-pcie-pll
23+
- amlogic,t7-mpll
24+
- amlogic,t7-hdmi-pll
25+
- amlogic,t7-mclk-pll
26+
27+
reg:
28+
maxItems: 1
29+
30+
'#clock-cells':
31+
const: 1
32+
33+
clocks:
34+
items:
35+
- description: mclk pll input oscillator gate
36+
- description: oscillator input clock source for mclk_sel_0
37+
- description: fixed input clock source for mclk_sel_0
38+
minItems: 1
39+
40+
clock-names:
41+
items:
42+
- const: in0
43+
- const: in1
44+
- const: in2
45+
minItems: 1
46+
47+
required:
48+
- compatible
49+
- '#clock-cells'
50+
- reg
51+
- clocks
52+
- clock-names
53+
54+
allOf:
55+
- if:
56+
properties:
57+
compatible:
58+
contains:
59+
const: amlogic,t7-mclk-pll
60+
61+
then:
62+
properties:
63+
clocks:
64+
minItems: 3
65+
66+
clock-names:
67+
minItems: 3
68+
69+
- if:
70+
properties:
71+
compatible:
72+
contains:
73+
enum:
74+
- amlogic,t7-gp0-pll
75+
- amlogic,t7-gp1--pll
76+
- amlogic,t7-hifi-pll
77+
- amlogic,t7-pcie-pll
78+
- amlogic,t7-mpll
79+
- amlogic,t7-hdmi-pll
80+
81+
then:
82+
properties:
83+
clocks:
84+
maxItems: 1
85+
86+
clock-names:
87+
maxItems: 1
88+
89+
additionalProperties: false
90+
91+
examples:
92+
- |
93+
apb {
94+
#address-cells = <2>;
95+
#size-cells = <2>;
96+
97+
clock-controller@8080 {
98+
compatible = "amlogic,t7-gp0-pll";
99+
reg = <0 0x8080 0 0x20>;
100+
clocks = <&scmi_clk 2>;
101+
clock-names = "in0";
102+
#clock-cells = <1>;
103+
};
104+
105+
clock-controller@8300 {
106+
compatible = "amlogic,t7-mclk-pll";
107+
reg = <0 0x8300 0 0x18>;
108+
clocks = <&scmi_clk 2>,
109+
<&xtal>,
110+
<&scmi_clk 31>;
111+
clock-names = "in0", "in1", "in2";
112+
#clock-cells = <1>;
113+
};
114+
};

‎Documentation/devicetree/bindings/clock/google,gs101-clock.yaml‎

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,11 @@ properties:
5353
reg:
5454
maxItems: 1
5555

56+
samsung,sysreg:
57+
$ref: /schemas/types.yaml#/definitions/phandle
58+
description:
59+
Phandle to system registers interface.
60+
5661
required:
5762
- compatible
5863
- "#clock-cells"
@@ -185,6 +190,18 @@ allOf:
185190
- const: bus
186191
- const: ip
187192

193+
- if:
194+
properties:
195+
compatible:
196+
contains:
197+
const: google,gs101-cmu-top
198+
then:
199+
properties:
200+
samsung,sysreg: false
201+
else:
202+
required:
203+
- samsung,sysreg
204+
188205
additionalProperties: false
189206

190207
examples:
@@ -194,7 +211,7 @@ examples:
194211
195212
cmu_top: clock-controller@1e080000 {
196213
compatible = "google,gs101-cmu-top";
197-
reg = <0x1e080000 0x8000>;
214+
reg = <0x1e080000 0x10000>;
198215
#clock-cells = <1>;
199216
clocks = <&ext_24_5m>;
200217
clock-names = "oscclk";

‎Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -14,11 +14,9 @@ maintainers:
1414

1515
properties:
1616
compatible:
17-
oneOf:
18-
- items:
19-
- const: mediatek,mt7622-pciesys
20-
- const: syscon
21-
- const: mediatek,mt7629-pciesys
17+
enum:
18+
- mediatek,mt7622-pciesys
19+
- mediatek,mt7629-pciesys
2220

2321
reg:
2422
maxItems: 1
@@ -40,7 +38,7 @@ additionalProperties: false
4038
examples:
4139
- |
4240
clock-controller@1a100800 {
43-
compatible = "mediatek,mt7622-pciesys", "syscon";
41+
compatible = "mediatek,mt7622-pciesys";
4442
reg = <0x1a100800 0x1000>;
4543
#clock-cells = <1>;
4644
#reset-cells = <1>;

‎Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,11 @@ description: |
1717
1818
properties:
1919
compatible:
20-
const: microchip,mpfs-ccc
20+
oneOf:
21+
- items:
22+
- const: microchip,pic64gx-ccc
23+
- const: microchip,mpfs-ccc
24+
- const: microchip,mpfs-ccc
2125

2226
reg:
2327
items:

‎Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml‎

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,11 @@ description: |
1919
2020
properties:
2121
compatible:
22-
const: microchip,mpfs-clkcfg
22+
oneOf:
23+
- items:
24+
- const: microchip,pic64gx-clkcfg
25+
- const: microchip,mpfs-clkcfg
26+
- const: microchip,mpfs-clkcfg
2327

2428
reg:
2529
oneOf:
@@ -69,6 +73,16 @@ required:
6973
- clocks
7074
- '#clock-cells'
7175

76+
if:
77+
properties:
78+
compatible:
79+
contains:
80+
const: microchip,pic64gx-clkcfg
81+
then:
82+
properties:
83+
reg:
84+
maxItems: 1
85+
7286
additionalProperties: false
7387

7488
examples:

‎Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
55
$schema: http://devicetree.org/meta-schemas/core.yaml#
66

7-
title: Qualcomm Global Clock & Reset Controller on MSM8953
7+
title: Qualcomm Global Clock & Reset Controller on MSM8937, MSM8940, MSM8953 and SDM439
88

99
maintainers:
1010
- Adam Skladowski <a_skl39@protonmail.com>
@@ -13,7 +13,7 @@ maintainers:
1313

1414
description: |
1515
Qualcomm global clock control module provides the clocks, resets and power
16-
domains on MSM8937 or MSM8953.
16+
domains on MSM8937, MSM8940, MSM8953 or SDM439.
1717
1818
See also::
1919
include/dt-bindings/clock/qcom,gcc-msm8917.h
@@ -23,7 +23,9 @@ properties:
2323
compatible:
2424
enum:
2525
- qcom,gcc-msm8937
26+
- qcom,gcc-msm8940
2627
- qcom,gcc-msm8953
28+
- qcom,gcc-sdm439
2729

2830
clocks:
2931
items:

0 commit comments

Comments
 (0)