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Merge branches 'clk-aspeed' and 'clk-qcom' into clk-next
* clk-aspeed: clk: aspeed: Add reset for HACE/VIDEO dt-bindings: clock: aspeed: Add VIDEO reset definition clk: aspeed: add AST2700 clock driver MAINTAINERS: Add entry for ASPEED clock drivers. clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory. * clk-qcom: (49 commits) clk: qcom: sm8750: Constify 'qcom_cc_desc' in SM8750 camcc clk: qcom: gfx3d: add parent to parent request map clk: qcom: dispcc-sm7150: Fix dispcc_mdss_pclk1_clk_src clk: qcom: dispcc-sdm845: Enable parents for pixel clocks clk: qcom: regmap-divider: convert from divider_round_rate() to divider_determine_rate() clk: qcom: regmap-divider: convert from divider_ro_round_rate() to divider_ro_determine_rate() clk: qcom: alpha-pll: convert from divider_round_rate() to divider_determine_rate() clk: qcom: Add support for GPUCC and GXCLK for Kaanapali clk: qcom: Add support for VideoCC driver for Kaanapali clk: qcom: camcc: Add support for camera clock controller for Kaanapali clk: qcom: dispcc: Add support for display clock controller Kaanapali clk: qcom: clk-alpha-pll: Add support for controlling Pongo EKO_T PLL clk: qcom: clk-alpha-pll: Update the PLL support for cal_l clk: qcom: camcc: Add camera clock controller driver for SM8750 SoC clk: qcom: clk-alpha-pll: Add support for controlling Rivian PLL dt-bindings: clock: qcom: document the Kaanapali GPU Clock Controller dt-bindings: clock: qcom: Add Kaanapali video clock controller dt-bindings: clock: qcom: Add support for CAMCC for Kaanapali dt-bindings: clock: qcom: document Kaanapali DISPCC clock controller dt-bindings: clock: qcom: Add camera clock controller for SM8750 SoC ...
3 parents a612d3d + 5f35b48 + 7fbabe8 commit 5921ae2

60 files changed

Lines changed: 15598 additions & 93 deletions

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‎Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml‎

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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on MSM8953
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title: Qualcomm Global Clock & Reset Controller on MSM8937, MSM8940, MSM8953 and SDM439
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maintainers:
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- Adam Skladowski <a_skl39@protonmail.com>
@@ -13,7 +13,7 @@ maintainers:
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on MSM8937 or MSM8953.
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domains on MSM8937, MSM8940, MSM8953 or SDM439.
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See also::
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include/dt-bindings/clock/qcom,gcc-msm8917.h
@@ -23,7 +23,9 @@ properties:
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compatible:
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enum:
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- qcom,gcc-msm8937
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- qcom,gcc-msm8940
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- qcom,gcc-msm8953
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- qcom,gcc-sdm439
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clocks:
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items:

‎Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,kaanapali-gxclkctl.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Graphics power domain Controller on Kaanapali
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9+
maintainers:
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- Taniya Das <taniya.das@oss.qualcomm.com>
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12+
description: |
13+
Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and
14+
Power domains (GDSC). This module provides the power domains control
15+
of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsystem.
16+
17+
See also:
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include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h
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20+
properties:
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compatible:
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enum:
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- qcom,kaanapali-gxclkctl
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power-domains:
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description:
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Power domains required for the clock controller to operate
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items:
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- description: GFX power domain
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- description: GMXC power domain
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- description: GPUCC(CX) power domain
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- power-domains
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- '#power-domain-cells'
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/power/qcom,rpmhpd.h>
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soc {
51+
#address-cells = <2>;
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#size-cells = <2>;
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clock-controller@3d64000 {
55+
compatible = "qcom,kaanapali-gxclkctl";
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reg = <0x0 0x03d64000 0x0 0x6000>;
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power-domains = <&rpmhpd RPMHPD_GFX>,
58+
<&rpmhpd RPMHPD_GMXC>,
59+
<&gpucc 0>;
60+
#power-domain-cells = <1>;
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};
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};
63+
...

‎Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml‎

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@@ -9,23 +9,32 @@ title: Qualcomm Camera Clock & Reset Controller on SM8450
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maintainers:
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- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
1111
- Jagadeesh Kona <quic_jkona@quicinc.com>
12+
- Taniya Das <taniya.das@oss.qualcomm.com>
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description: |
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Qualcomm camera clock control module provides the clocks, resets and power
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domains on SM8450.
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1718
See also:
19+
include/dt-bindings/clock/qcom,kaanapali-camcc.h
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include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h
1821
include/dt-bindings/clock/qcom,sm8450-camcc.h
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include/dt-bindings/clock/qcom,sm8550-camcc.h
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include/dt-bindings/clock/qcom,sm8650-camcc.h
24+
include/dt-bindings/clock/qcom,sm8750-cambistmclkcc.h
25+
include/dt-bindings/clock/qcom,sm8750-camcc.h
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properties:
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compatible:
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enum:
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- qcom,kaanapali-cambistmclkcc
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- qcom,kaanapali-camcc
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- qcom,sm8450-camcc
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- qcom,sm8475-camcc
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- qcom,sm8550-camcc
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- qcom,sm8650-camcc
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- qcom,sm8750-cambistmclkcc
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- qcom,sm8750-camcc
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clocks:
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items:
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compatible:
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contains:
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enum:
75+
- qcom,kaanapali-cambistmclkcc
76+
- qcom,kaanapali-camcc
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- qcom,sc8280xp-camcc
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- qcom,sm8450-camcc
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- qcom,sm8550-camcc

‎Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml‎

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domains on Qualcomm SoCs.
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See also::
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include/dt-bindings/clock/qcom,kaanapali-gpucc.h
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include/dt-bindings/clock/qcom,milos-gpucc.h
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include/dt-bindings/clock/qcom,sar2130p-gpucc.h
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include/dt-bindings/clock/qcom,sm4450-gpucc.h
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properties:
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compatible:
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enum:
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- qcom,kaanapali-gpucc
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- qcom,milos-gpucc
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- qcom,sar2130p-gpucc
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- qcom,sm4450-gpucc

‎Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml‎

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domains on SM8450.
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See also:
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include/dt-bindings/clock/qcom,kaanapali-videocc.h
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include/dt-bindings/clock/qcom,sm8450-videocc.h
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include/dt-bindings/clock/qcom,sm8650-videocc.h
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include/dt-bindings/clock/qcom,sm8750-videocc.h
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properties:
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compatible:
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enum:
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- qcom,kaanapali-videocc
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- qcom,sm8450-videocc
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- qcom,sm8475-videocc
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- qcom,sm8550-videocc
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compatible:
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contains:
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enum:
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- qcom,kaanapali-videocc
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- qcom,sm8450-videocc
6568
- qcom,sm8550-videocc
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- qcom,sm8750-videocc

‎Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml‎

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domains on SM8550, SM8650, SM8750 and few other platforms.
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See also:
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- include/dt-bindings/clock/qcom,kaanapali-dispcc.h
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- include/dt-bindings/clock/qcom,sm8550-dispcc.h
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- include/dt-bindings/clock/qcom,sm8650-dispcc.h
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- include/dt-bindings/clock/qcom,sm8750-dispcc.h
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properties:
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compatible:
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enum:
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- qcom,kaanapali-dispcc
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- qcom,sar2130p-dispcc
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- qcom,sm8550-dispcc
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- qcom,sm8650-dispcc

‎Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml‎

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- description: USB4_1 PHY max PIPE clock source
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- description: USB4_2 PHY PCIE PIPE clock source
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- description: USB4_2 PHY max PIPE clock source
65+
- description: UFS PHY RX Symbol 0 clock source
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- description: UFS PHY RX Symbol 1 clock source
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- description: UFS PHY TX Symbol 0 clock source
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power-domains:
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description:
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<&usb4_1_phy_pcie_pipe_clk>,
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<&usb4_1_phy_max_pipe_clk>,
123126
<&usb4_2_phy_pcie_pipe_clk>,
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<&usb4_2_phy_max_pipe_clk>;
127+
<&usb4_2_phy_max_pipe_clk>,
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<&ufs_phy_rx_symbol_0>,
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<&ufs_phy_rx_symbol_1>,
130+
<&ufs_phy_tx_symbol_0>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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#clock-cells = <1>;
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#reset-cells = <1>;

‎MAINTAINERS‎

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@@ -3836,6 +3836,15 @@ L: rust-for-linux@vger.kernel.org
38363836
S: Maintained
38373837
F: drivers/net/phy/ax88796b_rust.rs
38383838

3839+
ARM/ASPEED CLOCK SUPPORT
3840+
M: Ryan Chen <ryan_chen@aspeedtech.com>
3841+
R: Joel Stanley <joel@jms.id.au>
3842+
L: linux-clk@vger.kernel.org
3843+
L: linux-aspeed@lists.ozlabs.org
3844+
S: Maintained
3845+
F: Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
3846+
F: drivers/clk/aspeed/
3847+
38393848
ASPEED CRYPTO DRIVER
38403849
M: Neal Liu <neal_liu@aspeedtech.com>
38413850
L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)

‎drivers/clk/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -284,18 +284,6 @@ config COMMON_CLK_LAN966X
284284
LAN966X SoC. GCK generates and supplies clock to various peripherals
285285
within the SoC.
286286

287-
config COMMON_CLK_ASPEED
288-
bool "Clock driver for Aspeed BMC SoCs"
289-
depends on ARCH_ASPEED || COMPILE_TEST
290-
default ARCH_ASPEED
291-
select MFD_SYSCON
292-
select RESET_CONTROLLER
293-
help
294-
This driver supports the SoC clocks on the Aspeed BMC platforms.
295-
296-
The G4 and G5 series, including the ast2400 and ast2500, are supported
297-
by this driver.
298-
299287
config COMMON_CLK_S2MPS11
300288
tristate "Clock driver for S2MPS1X/S5M8767 MFD"
301289
depends on MFD_SEC_CORE || COMPILE_TEST
@@ -513,6 +501,7 @@ config COMMON_CLK_RPMI
513501

514502
source "drivers/clk/actions/Kconfig"
515503
source "drivers/clk/analogbits/Kconfig"
504+
source "drivers/clk/aspeed/Kconfig"
516505
source "drivers/clk/baikal-t1/Kconfig"
517506
source "drivers/clk/bcm/Kconfig"
518507
source "drivers/clk/hisilicon/Kconfig"

‎drivers/clk/Makefile‎

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@@ -62,8 +62,6 @@ obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
6262
obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o
6363
obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o
6464
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
65-
obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
66-
obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o
6765
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
6866
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
6967
obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o
@@ -114,6 +112,7 @@ obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
114112
# please keep this section sorted lexicographically by directory path name
115113
obj-y += actions/
116114
obj-y += analogbits/
115+
obj-y += aspeed/
117116
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
118117
obj-$(CONFIG_ARCH_ARTPEC) += axis/
119118
obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/

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