Merge branches 'clk-imx', 'clk-divider', 'clk-rockchip' and 'clk-microchip' into clk-next

* clk-imx:
  clk: imx: fracn-gppll: Add 241.90 MHz Support
  clk: imx: fracn-gppll: Add 332.60 MHz Support

* clk-divider:
  rtc: ac100: convert from divider_round_rate() to divider_determine_rate()
  clk: zynqmp: divider: convert from divider_round_rate() to divider_determine_rate()
  clk: x86: cgu: convert from divider_round_rate() to divider_determine_rate()
  clk: versaclock3: convert from divider_round_rate() to divider_determine_rate()
  clk: stm32: stm32-core: convert from divider_round_rate_parent() to divider_determine_rate()
  clk: stm32: stm32-core: convert from divider_ro_round_rate() to divider_ro_determine_rate()
  clk: sprd: div: convert from divider_round_rate() to divider_determine_rate()
  clk: sophgo: sg2042-clkgen: convert from divider_round_rate() to divider_determine_rate()
  clk: nxp: lpc32xx: convert from divider_round_rate() to divider_determine_rate()
  clk: nuvoton: ma35d1-divider: convert from divider_round_rate() to divider_determine_rate()
  clk: milbeaut: convert from divider_round_rate() to divider_determine_rate()
  clk: milbeaut: convert from divider_ro_round_rate() to divider_ro_determine_rate()
  clk: loongson1: convert from divider_round_rate() to divider_determine_rate()
  clk: hisilicon: clkdivider-hi6220: convert from divider_round_rate() to divider_determine_rate()
  clk: bm1880: convert from divider_round_rate() to divider_determine_rate()
  clk: bm1880: convert from divider_ro_round_rate() to divider_ro_determine_rate()
  clk: actions: owl-divider: convert from divider_round_rate() to divider_determine_rate()
  clk: actions: owl-composite: convert from owl_divider_helper_round_rate() to divider_determine_rate()
  clk: sunxi-ng: convert from divider_round_rate_parent() to divider_determine_rate()
  clk: sophgo: cv18xx-ip: convert from divider_round_rate() to divider_determine_rate()

* clk-rockchip:
  clk: rockchip: Fix error pointer check after rockchip_clk_register_gate_link()

* clk-microchip:
  dt-bindings: clock: mpfs-clkcfg: Add pic64gx compatibility
  dt-bindings: clock: mpfs-ccc: Add pic64gx compatibility
  clk: microchip: drop POLARFIRE from ARCH_MICROCHIP_POLARFIRE
  clk: microchip: core: remove unused include asm/traps.h
  clk: microchip: core: correct return value on *_get_parent()
  clk: microchip: core: remove duplicate determine_rate on pic32_sclk_ops

Author: bebarino

Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml

@@ -17,7 +17,11 @@ description: |
 
 properties:
   compatible:
-    const: microchip,mpfs-ccc
+    oneOf:
+      - items:
+          - const: microchip,pic64gx-ccc
+          - const: microchip,mpfs-ccc
+      - const: microchip,mpfs-ccc
 
   reg:
     items:

Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml

@@ -19,7 +19,11 @@ description: |
 
 properties:
   compatible:
-    const: microchip,mpfs-clkcfg
+    oneOf:
+      - items:
+          - const: microchip,pic64gx-clkcfg
+          - const: microchip,mpfs-clkcfg
+      - const: microchip,mpfs-clkcfg
 
   reg:
     oneOf:
@@ -69,6 +73,16 @@ required:
   - clocks
   - '#clock-cells'
 
+if:
+  properties:
+    compatible:
+      contains:
+        const: microchip,pic64gx-clkcfg
+then:
+  properties:
+    reg:
+      maxItems: 1
+
 additionalProperties: false
 
 examples:

drivers/clk/actions/owl-composite.c

@@ -57,15 +57,10 @@ static int owl_comp_div_determine_rate(struct clk_hw *hw,
 				       struct clk_rate_request *req)
 {
 	struct owl_composite *comp = hw_to_owl_comp(hw);
-	long rate;
-
-	rate = owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,
-					     req->rate, &req->best_parent_rate);
-	if (rate < 0)
-		return rate;
+	struct owl_divider_hw *div = &comp->rate.div_hw;
 
-	req->rate = rate;
-	return 0;
+	return divider_determine_rate(&comp->common.hw, req, div->table,
+				      div->width, div->div_flags);
 }
 
 static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw,

drivers/clk/actions/owl-divider.c

@@ -13,26 +13,13 @@
 
 #include "owl-divider.h"
 
-long owl_divider_helper_round_rate(struct owl_clk_common *common,
-				const struct owl_divider_hw *div_hw,
-				unsigned long rate,
-				unsigned long *parent_rate)
-{
-	return divider_round_rate(&common->hw, rate, parent_rate,
-				  div_hw->table, div_hw->width,
-				  div_hw->div_flags);
-}
-
 static int owl_divider_determine_rate(struct clk_hw *hw,
 				      struct clk_rate_request *req)
 {
 	struct owl_divider *div = hw_to_owl_divider(hw);
 
-	req->rate = owl_divider_helper_round_rate(&div->common, &div->div_hw,
-						  req->rate,
-						  &req->best_parent_rate);
-
-	return 0;
+	return divider_determine_rate(hw, req, div->div_hw.table,
+				      div->div_hw.width, div->div_hw.div_flags);
 }
 
 unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,

drivers/clk/actions/owl-divider.h

@@ -56,11 +56,6 @@ static inline struct owl_divider *hw_to_owl_divider(struct clk_hw *hw)
 	return container_of(common, struct owl_divider, common);
 }
 
-long owl_divider_helper_round_rate(struct owl_clk_common *common,
-				const struct owl_divider_hw *div_hw,
-				unsigned long rate,
-				unsigned long *parent_rate);
-
 unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,
 					 const struct owl_divider_hw *div_hw,
 					 unsigned long parent_rate);

drivers/clk/clk-bm1880.c

@@ -621,18 +621,11 @@ static int bm1880_clk_div_determine_rate(struct clk_hw *hw,
 		val = readl(reg_addr) >> div->shift;
 		val &= clk_div_mask(div->width);
 
-		req->rate = divider_ro_round_rate(hw, req->rate,
-						  &req->best_parent_rate,
-						  div->table,
-						  div->width, div->flags, val);
-
-		return 0;
+		return divider_ro_determine_rate(hw, req, div->table,
+						 div->width, div->flags, val);
 	}
 
-	req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
-				       div->table, div->width, div->flags);
-
-	return 0;
+	return divider_determine_rate(hw, req, div->table, div->width, div->flags);
 }
 
 static int bm1880_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/clk-loongson1.c

@@ -99,10 +99,7 @@ static int ls1x_divider_determine_rate(struct clk_hw *hw,
 	struct ls1x_clk *ls1x_clk = to_ls1x_clk(hw);
 	const struct ls1x_clk_div_data *d = ls1x_clk->data;
 
-	req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
-				       d->table, d->width, d->flags);
-
-	return 0;
+	return divider_determine_rate(hw, req, d->table, d->width, d->flags);
 }
 
 static int ls1x_divider_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/clk-milbeaut.c

@@ -398,19 +398,12 @@ static int m10v_clk_divider_determine_rate(struct clk_hw *hw,
 		val = readl(divider->reg) >> divider->shift;
 		val &= clk_div_mask(divider->width);
 
-		req->rate = divider_ro_round_rate(hw, req->rate,
-						  &req->best_parent_rate,
-						  divider->table,
-						  divider->width,
-						  divider->flags, val);
-
-		return 0;
+		return divider_ro_determine_rate(hw, req, divider->table,
+						 divider->width, divider->flags,
+						 val);
 	}
 
-	req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
-				       divider->table, divider->width, divider->flags);
-
-	return 0;
+	return divider_determine_rate(hw, req, divider->table, divider->width, divider->flags);
 }
 
 static int m10v_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/clk-versaclock3.c

@@ -523,11 +523,8 @@ static int vc3_div_determine_rate(struct clk_hw *hw,
 		return 0;
 	}
 
-	req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
-				       div_data->table,
-				       div_data->width, div_data->flags);
-
-	return 0;
+	return divider_determine_rate(hw, req, div_data->table, div_data->width,
+				      div_data->flags);
 }
 
 static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate,

drivers/clk/hisilicon/clkdivider-hi6220.c

@@ -60,10 +60,8 @@ static int hi6220_clkdiv_determine_rate(struct clk_hw *hw,
 {
 	struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw);
 
-	req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, dclk->table,
-				       dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
-
-	return 0;
+	return divider_determine_rate(hw, req, dclk->table, dclk->width,
+				      CLK_DIVIDER_ROUND_CLOSEST);
 }
 
 static int hi6220_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate,