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Merge branches 'clk-amlogic', 'clk-thead', 'clk-mediatek' and 'clk-samsung' into clk-next
* clk-amlogic: clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro clk: meson: g12a: Limit the HDMI PLL OD to /4 clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs clk: amlogic: remove potentially unsafe flags from S4 video clocks clk: amlogic: add video-related clocks for S4 SoC dt-bindings: clock: add video clock indices for Amlogic S4 SoC clk: meson: t7: add t7 clock peripherals controller driver clk: meson: t7: add support for the T7 SoC PLL clock dt-bindings: clock: add Amlogic T7 peripherals clock controller dt-bindings: clock: add Amlogic T7 SCMI clock controller dt-bindings: clock: add Amlogic T7 PLL clock controller * clk-thead: clk: thead: th1520-ap: Support CPU frequency scaling clk: thead: th1520-ap: Add macro to define multiplexers with flags clk: thead: th1520-ap: Support setting PLL rates clk: thead: th1520-ap: Add C910 bus clock clk: thead: th1520-ap: Poll for PLL lock and wait for stability dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock * clk-mediatek: Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc" clk: mediatek: Fix error handling in runtime PM setup clk: mediatek: don't select clk-mt8192 for all ARM64 builds clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks clk: mediatek: Refactor pllfh registration to pass device clk: mediatek: Pass device to clk_hw_register for PLLs clk: mediatek: Refactor pll registration to pass device clk: Respect CLK_OPS_PARENT_ENABLE during recalc dt-bindings: clock: mediatek,mt7622-pciesys: Remove syscon compatible clk: mediatek: Drop __initconst from gates * clk-samsung: clk: samsung: gs101: add support for Display Process Unit (DPU) clocks dt-bindings: samsung: exynos-sysreg: add gs101 dpu compatible dt-bindings: clock: google,gs101-clock: Add DPU clock management unit dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering clk: samsung: fix sysreg save/restore when PM is enabled for CMU clk: samsung: avoid warning message on legacy Exynos (auto clock gating) clk: samsung: gs101: Enable auto_clock_gate mode for each gs101 CMU clk: samsung: Implement automatic clock gating mode for CMUs dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required clk: samsung: exynosautov920: add clock support dt-bindings: clock: exynosautov920: add MFD clock definitions
5 parents 16c3c4e + d8b210f + d5798ed + 448b50b + 847eaf0 commit b675697

67 files changed

Lines changed: 4426 additions & 145 deletions

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‎Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml‎

Lines changed: 116 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,116 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
3+
%YAML 1.2
4+
---
5+
$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml#
6+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7+
8+
title: Amlogic T7 Peripherals Clock Controller
9+
10+
maintainers:
11+
- Neil Armstrong <neil.armstrong@linaro.org>
12+
- Jerome Brunet <jbrunet@baylibre.com>
13+
- Xianwei Zhao <xianwei.zhao@amlogic.com>
14+
- Jian Hu <jian.hu@amlogic.com>
15+
16+
properties:
17+
compatible:
18+
const: amlogic,t7-peripherals-clkc
19+
20+
reg:
21+
maxItems: 1
22+
23+
'#clock-cells':
24+
const: 1
25+
26+
clocks:
27+
minItems: 14
28+
items:
29+
- description: input oscillator
30+
- description: input sys clk
31+
- description: input fixed pll
32+
- description: input fclk div 2
33+
- description: input fclk div 2p5
34+
- description: input fclk div 3
35+
- description: input fclk div 4
36+
- description: input fclk div 5
37+
- description: input fclk div 7
38+
- description: input hifi pll
39+
- description: input gp0 pll
40+
- description: input gp1 pll
41+
- description: input mpll1
42+
- description: input mpll2
43+
- description: external input rmii oscillator (optional)
44+
- description: input video pll0 (optional)
45+
- description: external pad input for rtc (optional)
46+
47+
clock-names:
48+
minItems: 14
49+
items:
50+
- const: xtal
51+
- const: sys
52+
- const: fix
53+
- const: fdiv2
54+
- const: fdiv2p5
55+
- const: fdiv3
56+
- const: fdiv4
57+
- const: fdiv5
58+
- const: fdiv7
59+
- const: hifi
60+
- const: gp0
61+
- const: gp1
62+
- const: mpll1
63+
- const: mpll2
64+
- const: ext_rmii
65+
- const: vid_pll0
66+
- const: ext_rtc
67+
68+
required:
69+
- compatible
70+
- '#clock-cells'
71+
- reg
72+
- clocks
73+
- clock-names
74+
75+
additionalProperties: false
76+
77+
examples:
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- |
79+
apb {
80+
#address-cells = <2>;
81+
#size-cells = <2>;
82+
83+
clkc_periphs:clock-controller@0 {
84+
compatible = "amlogic,t7-peripherals-clkc";
85+
reg = <0 0x0 0 0x1c8>;
86+
#clock-cells = <1>;
87+
clocks = <&xtal>,
88+
<&scmi_clk 13>,
89+
<&scmi_clk 16>,
90+
<&scmi_clk 18>,
91+
<&scmi_clk 20>,
92+
<&scmi_clk 22>,
93+
<&scmi_clk 24>,
94+
<&scmi_clk 26>,
95+
<&scmi_clk 28>,
96+
<&hifi 1>,
97+
<&gp0 1>,
98+
<&gp1 1>,
99+
<&mpll 4>,
100+
<&mpll 6>;
101+
clock-names = "xtal",
102+
"sys",
103+
"fix",
104+
"fdiv2",
105+
"fdiv2p5",
106+
"fdiv3",
107+
"fdiv4",
108+
"fdiv5",
109+
"fdiv7",
110+
"hifi",
111+
"gp0",
112+
"gp1",
113+
"mpll1",
114+
"mpll2";
115+
};
116+
};

‎Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,114 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
3+
%YAML 1.2
4+
---
5+
$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
6+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7+
8+
title: Amlogic T7 PLL Clock Control Controller
9+
10+
maintainers:
11+
- Neil Armstrong <neil.armstrong@linaro.org>
12+
- Jerome Brunet <jbrunet@baylibre.com>
13+
- Jian Hu <jian.hu@amlogic.com>
14+
- Xianwei Zhao <xianwei.zhao@amlogic.com>
15+
16+
properties:
17+
compatible:
18+
enum:
19+
- amlogic,t7-gp0-pll
20+
- amlogic,t7-gp1-pll
21+
- amlogic,t7-hifi-pll
22+
- amlogic,t7-pcie-pll
23+
- amlogic,t7-mpll
24+
- amlogic,t7-hdmi-pll
25+
- amlogic,t7-mclk-pll
26+
27+
reg:
28+
maxItems: 1
29+
30+
'#clock-cells':
31+
const: 1
32+
33+
clocks:
34+
items:
35+
- description: mclk pll input oscillator gate
36+
- description: oscillator input clock source for mclk_sel_0
37+
- description: fixed input clock source for mclk_sel_0
38+
minItems: 1
39+
40+
clock-names:
41+
items:
42+
- const: in0
43+
- const: in1
44+
- const: in2
45+
minItems: 1
46+
47+
required:
48+
- compatible
49+
- '#clock-cells'
50+
- reg
51+
- clocks
52+
- clock-names
53+
54+
allOf:
55+
- if:
56+
properties:
57+
compatible:
58+
contains:
59+
const: amlogic,t7-mclk-pll
60+
61+
then:
62+
properties:
63+
clocks:
64+
minItems: 3
65+
66+
clock-names:
67+
minItems: 3
68+
69+
- if:
70+
properties:
71+
compatible:
72+
contains:
73+
enum:
74+
- amlogic,t7-gp0-pll
75+
- amlogic,t7-gp1--pll
76+
- amlogic,t7-hifi-pll
77+
- amlogic,t7-pcie-pll
78+
- amlogic,t7-mpll
79+
- amlogic,t7-hdmi-pll
80+
81+
then:
82+
properties:
83+
clocks:
84+
maxItems: 1
85+
86+
clock-names:
87+
maxItems: 1
88+
89+
additionalProperties: false
90+
91+
examples:
92+
- |
93+
apb {
94+
#address-cells = <2>;
95+
#size-cells = <2>;
96+
97+
clock-controller@8080 {
98+
compatible = "amlogic,t7-gp0-pll";
99+
reg = <0 0x8080 0 0x20>;
100+
clocks = <&scmi_clk 2>;
101+
clock-names = "in0";
102+
#clock-cells = <1>;
103+
};
104+
105+
clock-controller@8300 {
106+
compatible = "amlogic,t7-mclk-pll";
107+
reg = <0 0x8300 0 0x18>;
108+
clocks = <&scmi_clk 2>,
109+
<&xtal>,
110+
<&scmi_clk 31>;
111+
clock-names = "in0", "in1", "in2";
112+
#clock-cells = <1>;
113+
};
114+
};

‎Documentation/devicetree/bindings/clock/google,gs101-clock.yaml‎

Lines changed: 38 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,10 @@ properties:
2929
enum:
3030
- google,gs101-cmu-top
3131
- google,gs101-cmu-apm
32-
- google,gs101-cmu-misc
32+
- google,gs101-cmu-dpu
3333
- google,gs101-cmu-hsi0
3434
- google,gs101-cmu-hsi2
35+
- google,gs101-cmu-misc
3536
- google,gs101-cmu-peric0
3637
- google,gs101-cmu-peric1
3738

@@ -52,6 +53,11 @@ properties:
5253
reg:
5354
maxItems: 1
5455

56+
samsung,sysreg:
57+
$ref: /schemas/types.yaml#/definitions/phandle
58+
description:
59+
Phandle to system registers interface.
60+
5561
required:
5662
- compatible
5763
- "#clock-cells"
@@ -77,6 +83,24 @@ allOf:
7783
items:
7884
- const: oscclk
7985

86+
- if:
87+
properties:
88+
compatible:
89+
contains:
90+
const: google,gs101-cmu-dpu
91+
92+
then:
93+
properties:
94+
clocks:
95+
items:
96+
- description: External reference clock (24.576 MHz)
97+
- description: DPU bus clock (from CMU_TOP)
98+
99+
clock-names:
100+
items:
101+
- const: oscclk
102+
- const: bus
103+
80104
- if:
81105
properties:
82106
compatible:
@@ -166,6 +190,18 @@ allOf:
166190
- const: bus
167191
- const: ip
168192

193+
- if:
194+
properties:
195+
compatible:
196+
contains:
197+
const: google,gs101-cmu-top
198+
then:
199+
properties:
200+
samsung,sysreg: false
201+
else:
202+
required:
203+
- samsung,sysreg
204+
169205
additionalProperties: false
170206

171207
examples:
@@ -175,7 +211,7 @@ examples:
175211
176212
cmu_top: clock-controller@1e080000 {
177213
compatible = "google,gs101-cmu-top";
178-
reg = <0x1e080000 0x8000>;
214+
reg = <0x1e080000 0x10000>;
179215
#clock-cells = <1>;
180216
clocks = <&ext_24_5m>;
181217
clock-names = "oscclk";

‎Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -14,11 +14,9 @@ maintainers:
1414

1515
properties:
1616
compatible:
17-
oneOf:
18-
- items:
19-
- const: mediatek,mt7622-pciesys
20-
- const: syscon
21-
- const: mediatek,mt7629-pciesys
17+
enum:
18+
- mediatek,mt7622-pciesys
19+
- mediatek,mt7629-pciesys
2220

2321
reg:
2422
maxItems: 1
@@ -40,7 +38,7 @@ additionalProperties: false
4038
examples:
4139
- |
4240
clock-controller@1a100800 {
43-
compatible = "mediatek,mt7622-pciesys", "syscon";
41+
compatible = "mediatek,mt7622-pciesys";
4442
reg = <0x1a100800 0x1000>;
4543
#clock-cells = <1>;
4644
#reset-cells = <1>;

‎Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ properties:
4040
- samsung,exynosautov920-cmu-hsi2
4141
- samsung,exynosautov920-cmu-m2m
4242
- samsung,exynosautov920-cmu-mfc
43+
- samsung,exynosautov920-cmu-mfd
4344
- samsung,exynosautov920-cmu-misc
4445
- samsung,exynosautov920-cmu-peric0
4546
- samsung,exynosautov920-cmu-peric1
@@ -268,6 +269,24 @@ allOf:
268269
- const: mfc
269270
- const: wfd
270271

272+
- if:
273+
properties:
274+
compatible:
275+
contains:
276+
const: samsung,exynosautov920-cmu-mfd
277+
278+
then:
279+
properties:
280+
clocks:
281+
items:
282+
- description: External reference clock (38.4 MHz)
283+
- description: CMU_MFD NOC clock (from CMU_TOP)
284+
285+
clock-names:
286+
items:
287+
- const: oscclk
288+
- const: noc
289+
271290
required:
272291
- compatible
273292
- "#clock-cells"

‎Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ properties:
1515
- items:
1616
- enum:
1717
- google,gs101-apm-sysreg
18+
- google,gs101-dpu-sysreg
1819
- google,gs101-hsi0-sysreg
1920
- google,gs101-hsi2-sysreg
2021
- google,gs101-misc-sysreg
@@ -92,6 +93,7 @@ allOf:
9293
compatible:
9394
contains:
9495
enum:
96+
- google,gs101-dpu-sysreg
9597
- google,gs101-hsi0-sysreg
9698
- google,gs101-hsi2-sysreg
9799
- google,gs101-misc-sysreg

‎drivers/clk/mediatek/Kconfig‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -820,7 +820,7 @@ config COMMON_CLK_MT8192
820820
depends on ARM64 || COMPILE_TEST
821821
select COMMON_CLK_MEDIATEK
822822
select COMMON_CLK_MEDIATEK_FHCTL
823-
default ARM64
823+
default ARM64 && ARCH_MEDIATEK
824824
help
825825
This driver supports MediaTek MT8192 basic clocks.
826826

‎drivers/clk/mediatek/clk-mt2701.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -978,7 +978,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
978978
if (!clk_data)
979979
return -ENOMEM;
980980

981-
mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
981+
mtk_clk_register_plls(&pdev->dev, apmixed_plls, ARRAY_SIZE(apmixed_plls),
982982
clk_data);
983983
mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
984984
clk_data);

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