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Merge tag 'clk-meson-v6.20-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver updates from Jerome Brunet: - Add support for Amlogic t7 clock controllers - Add video clocks on Amlogic s4 - HDMI PLL post divider fixes on Amlogic gx/g12 SoCs * tag 'clk-meson-v6.20-1' of https://github.com/BayLibre/clk-meson: clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro clk: meson: g12a: Limit the HDMI PLL OD to /4 clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs clk: amlogic: remove potentially unsafe flags from S4 video clocks clk: amlogic: add video-related clocks for S4 SoC dt-bindings: clock: add video clock indices for Amlogic S4 SoC clk: meson: t7: add t7 clock peripherals controller driver clk: meson: t7: add support for the T7 SoC PLL clock dt-bindings: clock: add Amlogic T7 peripherals clock controller dt-bindings: clock: add Amlogic T7 SCMI clock controller dt-bindings: clock: add Amlogic T7 PLL clock controller
2 parents 8f0b4cc + 2fe1ef4 commit d8b210f

13 files changed

Lines changed: 3180 additions & 13 deletions

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‎Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic T7 Peripherals Clock Controller
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Jerome Brunet <jbrunet@baylibre.com>
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- Xianwei Zhao <xianwei.zhao@amlogic.com>
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- Jian Hu <jian.hu@amlogic.com>
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properties:
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compatible:
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const: amlogic,t7-peripherals-clkc
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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minItems: 14
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items:
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- description: input oscillator
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- description: input sys clk
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- description: input fixed pll
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- description: input fclk div 2
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- description: input fclk div 2p5
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- description: input fclk div 3
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- description: input fclk div 4
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- description: input fclk div 5
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- description: input fclk div 7
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- description: input hifi pll
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- description: input gp0 pll
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- description: input gp1 pll
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- description: input mpll1
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- description: input mpll2
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- description: external input rmii oscillator (optional)
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- description: input video pll0 (optional)
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- description: external pad input for rtc (optional)
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clock-names:
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minItems: 14
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items:
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- const: xtal
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- const: sys
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- const: fix
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- const: fdiv2
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- const: fdiv2p5
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- const: fdiv3
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- const: fdiv4
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- const: fdiv5
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- const: fdiv7
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- const: hifi
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- const: gp0
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- const: gp1
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- const: mpll1
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- const: mpll2
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- const: ext_rmii
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- const: vid_pll0
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- const: ext_rtc
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required:
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- compatible
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- '#clock-cells'
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- reg
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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apb {
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#address-cells = <2>;
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#size-cells = <2>;
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clkc_periphs:clock-controller@0 {
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compatible = "amlogic,t7-peripherals-clkc";
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reg = <0 0x0 0 0x1c8>;
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#clock-cells = <1>;
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clocks = <&xtal>,
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<&scmi_clk 13>,
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<&scmi_clk 16>,
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<&scmi_clk 18>,
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<&scmi_clk 20>,
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<&scmi_clk 22>,
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<&scmi_clk 24>,
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<&scmi_clk 26>,
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<&scmi_clk 28>,
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<&hifi 1>,
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<&gp0 1>,
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<&gp1 1>,
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<&mpll 4>,
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<&mpll 6>;
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clock-names = "xtal",
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"sys",
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"fix",
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"fdiv2",
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"fdiv2p5",
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"fdiv3",
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"fdiv4",
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"fdiv5",
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"fdiv7",
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"hifi",
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"gp0",
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"gp1",
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"mpll1",
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"mpll2";
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};
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};

‎Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic T7 PLL Clock Control Controller
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Jerome Brunet <jbrunet@baylibre.com>
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- Jian Hu <jian.hu@amlogic.com>
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- Xianwei Zhao <xianwei.zhao@amlogic.com>
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properties:
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compatible:
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enum:
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- amlogic,t7-gp0-pll
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- amlogic,t7-gp1-pll
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- amlogic,t7-hifi-pll
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- amlogic,t7-pcie-pll
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- amlogic,t7-mpll
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- amlogic,t7-hdmi-pll
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- amlogic,t7-mclk-pll
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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items:
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- description: mclk pll input oscillator gate
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- description: oscillator input clock source for mclk_sel_0
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- description: fixed input clock source for mclk_sel_0
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minItems: 1
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clock-names:
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items:
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- const: in0
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- const: in1
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- const: in2
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minItems: 1
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required:
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- compatible
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- '#clock-cells'
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- reg
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: amlogic,t7-mclk-pll
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then:
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properties:
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clocks:
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minItems: 3
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clock-names:
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minItems: 3
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- if:
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properties:
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compatible:
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contains:
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enum:
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- amlogic,t7-gp0-pll
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- amlogic,t7-gp1--pll
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- amlogic,t7-hifi-pll
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- amlogic,t7-pcie-pll
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- amlogic,t7-mpll
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- amlogic,t7-hdmi-pll
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then:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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additionalProperties: false
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examples:
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- |
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apb {
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#address-cells = <2>;
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#size-cells = <2>;
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clock-controller@8080 {
98+
compatible = "amlogic,t7-gp0-pll";
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reg = <0 0x8080 0 0x20>;
100+
clocks = <&scmi_clk 2>;
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clock-names = "in0";
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#clock-cells = <1>;
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};
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clock-controller@8300 {
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compatible = "amlogic,t7-mclk-pll";
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reg = <0 0x8300 0 0x18>;
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clocks = <&scmi_clk 2>,
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<&xtal>,
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<&scmi_clk 31>;
111+
clock-names = "in0", "in1", "in2";
112+
#clock-cells = <1>;
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};
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};

‎drivers/clk/meson/Kconfig‎

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@@ -201,4 +201,32 @@ config COMMON_CLK_S4_PERIPHERALS
201201
help
202202
Support for the peripherals clock controller on Amlogic S805X2 and S905Y4
203203
devices, AKA S4. Say Y if you want S4 peripherals clock controller to work.
204+
205+
config COMMON_CLK_T7_PLL
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tristate "Amlogic T7 SoC PLL controller support"
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depends on ARM64
208+
default ARCH_MESON
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select COMMON_CLK_MESON_REGMAP
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select COMMON_CLK_MESON_CLKC_UTILS
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select COMMON_CLK_MESON_MPLL
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select COMMON_CLK_MESON_PLL
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imply COMMON_CLK_SCMI
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help
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Support for the PLL clock controller on Amlogic A311D2 based
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device, AKA T7. PLLs are required by most peripheral to operate.
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Say Y if you want T7 PLL clock controller to work.
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config COMMON_CLK_T7_PERIPHERALS
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tristate "Amlogic T7 SoC peripherals clock controller support"
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depends on ARM64
222+
default ARCH_MESON
223+
select COMMON_CLK_MESON_REGMAP
224+
select COMMON_CLK_MESON_CLKC_UTILS
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select COMMON_CLK_MESON_DUALDIV
226+
imply COMMON_CLK_SCMI
227+
imply COMMON_CLK_T7_PLL
228+
help
229+
Support for the peripherals clock controller on Amlogic A311D2 based
230+
device, AKA T7. Peripherals are required by most peripheral to operate.
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Say Y if you want T7 peripherals clock controller to work.
204232
endmenu

‎drivers/clk/meson/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -26,3 +26,5 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
2626
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
2727
obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
2828
obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o
29+
obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o
30+
obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) += t7-peripherals.o

‎drivers/clk/meson/g12a.c‎

Lines changed: 14 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -777,12 +777,23 @@ static struct clk_regmap g12a_hdmi_pll_dco = {
777777
},
778778
};
779779

780+
/*
781+
* G12/SM1 hdmi OD dividers are POWER_OF_TWO dividers but limited to /4.
782+
* A divider value of 3 should map to /8 but instead map /4 so ignore it.
783+
*/
784+
static const struct clk_div_table g12a_hdmi_pll_od_div_table[] = {
785+
{ .val = 0, .div = 1 },
786+
{ .val = 1, .div = 2 },
787+
{ .val = 2, .div = 4 },
788+
{ /* sentinel */ }
789+
};
790+
780791
static struct clk_regmap g12a_hdmi_pll_od = {
781792
.data = &(struct clk_regmap_div_data){
782793
.offset = HHI_HDMI_PLL_CNTL0,
783794
.shift = 16,
784795
.width = 2,
785-
.flags = CLK_DIVIDER_POWER_OF_TWO,
796+
.table = g12a_hdmi_pll_od_div_table,
786797
},
787798
.hw.init = &(struct clk_init_data){
788799
.name = "hdmi_pll_od",
@@ -800,7 +811,7 @@ static struct clk_regmap g12a_hdmi_pll_od2 = {
800811
.offset = HHI_HDMI_PLL_CNTL0,
801812
.shift = 18,
802813
.width = 2,
803-
.flags = CLK_DIVIDER_POWER_OF_TWO,
814+
.table = g12a_hdmi_pll_od_div_table,
804815
},
805816
.hw.init = &(struct clk_init_data){
806817
.name = "hdmi_pll_od2",
@@ -818,7 +829,7 @@ static struct clk_regmap g12a_hdmi_pll = {
818829
.offset = HHI_HDMI_PLL_CNTL0,
819830
.shift = 20,
820831
.width = 2,
821-
.flags = CLK_DIVIDER_POWER_OF_TWO,
832+
.table = g12a_hdmi_pll_od_div_table,
822833
},
823834
.hw.init = &(struct clk_init_data){
824835
.name = "hdmi_pll",

‎drivers/clk/meson/gxbb.c‎

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -349,12 +349,23 @@ static struct clk_regmap gxbb_hdmi_pll = {
349349
},
350350
};
351351

352+
/*
353+
* GXL hdmi OD dividers are POWER_OF_TWO dividers but limited to /4.
354+
* A divider value of 3 should map to /8 but instead map /4 so ignore it.
355+
*/
356+
static const struct clk_div_table gxl_hdmi_pll_od_div_table[] = {
357+
{ .val = 0, .div = 1 },
358+
{ .val = 1, .div = 2 },
359+
{ .val = 2, .div = 4 },
360+
{ /* sentinel */ }
361+
};
362+
352363
static struct clk_regmap gxl_hdmi_pll_od = {
353364
.data = &(struct clk_regmap_div_data){
354-
.offset = HHI_HDMI_PLL_CNTL + 8,
365+
.offset = HHI_HDMI_PLL_CNTL3,
355366
.shift = 21,
356367
.width = 2,
357-
.flags = CLK_DIVIDER_POWER_OF_TWO,
368+
.table = gxl_hdmi_pll_od_div_table,
358369
},
359370
.hw.init = &(struct clk_init_data){
360371
.name = "hdmi_pll_od",
@@ -369,10 +380,10 @@ static struct clk_regmap gxl_hdmi_pll_od = {
369380

370381
static struct clk_regmap gxl_hdmi_pll_od2 = {
371382
.data = &(struct clk_regmap_div_data){
372-
.offset = HHI_HDMI_PLL_CNTL + 8,
383+
.offset = HHI_HDMI_PLL_CNTL3,
373384
.shift = 23,
374385
.width = 2,
375-
.flags = CLK_DIVIDER_POWER_OF_TWO,
386+
.table = gxl_hdmi_pll_od_div_table,
376387
},
377388
.hw.init = &(struct clk_init_data){
378389
.name = "hdmi_pll_od2",
@@ -387,10 +398,10 @@ static struct clk_regmap gxl_hdmi_pll_od2 = {
387398

388399
static struct clk_regmap gxl_hdmi_pll = {
389400
.data = &(struct clk_regmap_div_data){
390-
.offset = HHI_HDMI_PLL_CNTL + 8,
401+
.offset = HHI_HDMI_PLL_CNTL3,
391402
.shift = 19,
392403
.width = 2,
393-
.flags = CLK_DIVIDER_POWER_OF_TWO,
404+
.table = gxl_hdmi_pll_od_div_table,
394405
},
395406
.hw.init = &(struct clk_init_data){
396407
.name = "hdmi_pll",

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