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konradybciorobclark
konradybcio
authored and
robclark
committed
drm/msm/a6xx: Add A740 support
A740 builds upon the A730 IP, shuffling some values and registers around. More differences will appear when things like BCL are implemented. adreno_is_a740_family is added in preparation for more A7xx GPUs, the logic checks will be valid resulting in smaller diffs. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559291/ Signed-off-by: Rob Clark <robdclark@chromium.org>
1 parent 9588d2f commit 1f8c29e

6 files changed

Lines changed: 201 additions & 38 deletions

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‎drivers/gpu/drm/msm/adreno/a6xx_gmu.c‎

Lines changed: 61 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -519,6 +519,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
519519
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
520520
struct platform_device *pdev = to_platform_device(gmu->dev);
521521
void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
522+
u32 seqmem0_drv0_reg = REG_A6XX_RSCC_SEQ_MEM_0_DRV0;
522523
void __iomem *seqptr = NULL;
523524
uint32_t pdc_address_offset;
524525
bool pdc_in_aop = false;
@@ -552,21 +553,26 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
552553
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
553554
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
554555
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
555-
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
556+
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4,
557+
adreno_is_a740_family(adreno_gpu) ? 0x80000021 : 0x80000000);
556558
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
557559
gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
558560
gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
559561
gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
560562
gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
561563

564+
/* The second spin of A7xx GPUs messed with some register offsets.. */
565+
if (adreno_is_a740_family(adreno_gpu))
566+
seqmem0_drv0_reg = REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740;
567+
562568
/* Load RSC sequencer uCode for sleep and wakeup */
563569
if (adreno_is_a650_family(adreno_gpu) ||
564570
adreno_is_a7xx(adreno_gpu)) {
565-
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
566-
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
567-
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
568-
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
569-
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
571+
gmu_write_rscc(gmu, seqmem0_drv0_reg, 0xeaaae5a0);
572+
gmu_write_rscc(gmu, seqmem0_drv0_reg + 1, 0xe1a1ebab);
573+
gmu_write_rscc(gmu, seqmem0_drv0_reg + 2, 0xa2e0a581);
574+
gmu_write_rscc(gmu, seqmem0_drv0_reg + 3, 0xecac82e2);
575+
gmu_write_rscc(gmu, seqmem0_drv0_reg + 4, 0x0020edad);
570576
} else {
571577
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
572578
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
@@ -764,8 +770,8 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
764770
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
765771
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
766772
u32 fence_range_lower, fence_range_upper;
773+
u32 chipid, chipid_min = 0;
767774
int ret;
768-
u32 chipid;
769775

770776
/* Vote veto for FAL10 */
771777
if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) {
@@ -824,16 +830,37 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
824830
*/
825831
gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);
826832

827-
/*
828-
* Note that the GMU has a slightly different layout for
829-
* chip_id, for whatever reason, so a bit of massaging
830-
* is needed. The upper 16b are the same, but minor and
831-
* patchid are packed in four bits each with the lower
832-
* 8b unused:
833-
*/
834-
chipid = adreno_gpu->chip_id & 0xffff0000;
835-
chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
836-
chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
833+
/* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */
834+
if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) {
835+
/* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */
836+
chipid = FIELD_PREP(GENMASK(31, 24), 0x7);
837+
838+
/*
839+
* The min part has a 1-1 mapping for each GPU SKU.
840+
* This chipid that the GMU expects corresponds to the "GENX_Y_Z" naming,
841+
* where X = major, Y = minor, Z = patchlevel, e.g. GEN7_2_1 for prod A740.
842+
*/
843+
if (adreno_is_a740(adreno_gpu))
844+
chipid_min = 2;
845+
else
846+
return -EINVAL;
847+
848+
chipid |= FIELD_PREP(GENMASK(23, 16), chipid_min);
849+
850+
/* Get the patchid (which may vary) from the device tree */
851+
chipid |= FIELD_PREP(GENMASK(15, 8), adreno_patchid(adreno_gpu));
852+
} else {
853+
/*
854+
* Note that the GMU has a slightly different layout for
855+
* chip_id, for whatever reason, so a bit of massaging
856+
* is needed. The upper 16b are the same, but minor and
857+
* patchid are packed in four bits each with the lower
858+
* 8b unused:
859+
*/
860+
chipid = adreno_gpu->chip_id & 0xffff0000;
861+
chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
862+
chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
863+
}
837864

838865
if (adreno_is_a7xx(adreno_gpu)) {
839866
gmu_write(gmu, REG_A6XX_GMU_GENERAL_10, chipid);
@@ -896,17 +923,23 @@ static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu)
896923

897924
static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
898925
{
899-
u32 val;
926+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
927+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
928+
u32 val, seqmem_off = 0;
929+
930+
/* The second spin of A7xx GPUs messed with some register offsets.. */
931+
if (adreno_is_a740_family(adreno_gpu))
932+
seqmem_off = 4;
900933

901934
/* Make sure there are no outstanding RPMh votes */
902-
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
903-
(val & 1), 100, 10000);
904-
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
905-
(val & 1), 100, 10000);
906-
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
907-
(val & 1), 100, 10000);
908-
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
909-
(val & 1), 100, 1000);
935+
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS + seqmem_off,
936+
val, (val & 1), 100, 10000);
937+
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS + seqmem_off,
938+
val, (val & 1), 100, 10000);
939+
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS + seqmem_off,
940+
val, (val & 1), 100, 10000);
941+
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off,
942+
val, (val & 1), 100, 1000);
910943
}
911944

912945
/* Force the GMU off in case it isn't responsive */
@@ -1010,7 +1043,8 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
10101043

10111044
/* Use a known rate to bring up the GMU */
10121045
clk_set_rate(gmu->core_clk, 200000000);
1013-
clk_set_rate(gmu->hub_clk, 150000000);
1046+
clk_set_rate(gmu->hub_clk, adreno_is_a740_family(adreno_gpu) ?
1047+
200000000 : 150000000);
10141048
ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
10151049
if (ret) {
10161050
pm_runtime_put(gmu->gxpd);

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 74 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -894,14 +894,72 @@ const struct adreno_reglist a730_hwcg[] = {
894894
{},
895895
};
896896

897+
const struct adreno_reglist a740_hwcg[] = {
898+
{ REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
899+
{ REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x22022222 },
900+
{ REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x003cf3cf },
901+
{ REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
902+
{ REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
903+
{ REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
904+
{ REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
905+
{ REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
906+
{ REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
907+
{ REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
908+
{ REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
909+
{ REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
910+
{ REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
911+
{ REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
912+
{ REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
913+
{ REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
914+
{ REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
915+
{ REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x00222222 },
916+
{ REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000444 },
917+
{ REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000222 },
918+
{ REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
919+
{ REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
920+
{ REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
921+
{ REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
922+
{ REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
923+
{ REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
924+
{ REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
925+
{ REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
926+
{ REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
927+
{ REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
928+
{ REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
929+
{ REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
930+
{ REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00222222 },
931+
{ REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
932+
{ REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
933+
{ REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
934+
{ REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
935+
{ REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
936+
{ REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000000 },
937+
{ REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
938+
{ REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00000000 },
939+
{ REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
940+
{ REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
941+
{ REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
942+
{ REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
943+
{ REG_A7XX_RBBM_CLOCK_HYST2_VFD, 0x00000000 },
944+
{ REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000222 },
945+
{ REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
946+
{ REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
947+
{ REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
948+
{ REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
949+
{ REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
950+
{ REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
951+
{ REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
952+
{},
953+
};
954+
897955
static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
898956
{
899957
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
900958
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
901959
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
902960
const struct adreno_reglist *reg;
903961
unsigned int i;
904-
u32 val, clock_cntl_on;
962+
u32 val, clock_cntl_on, cgc_mode;
905963

906964
if (!adreno_gpu->info->hwcg)
907965
return;
@@ -914,8 +972,10 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
914972
clock_cntl_on = 0x8aa8aa82;
915973

916974
if (adreno_is_a7xx(adreno_gpu)) {
975+
cgc_mode = adreno_is_a740_family(adreno_gpu) ? 0x20222 : 0x20000;
976+
917977
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
918-
state ? 0x20000 : 0);
978+
state ? cgc_mode : 0);
919979
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
920980
state ? 0x10111 : 0);
921981
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
@@ -1179,7 +1239,7 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
11791239
count = ARRAY_SIZE(a660_protect);
11801240
count_max = 48;
11811241
BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48);
1182-
} else if (adreno_is_a730(adreno_gpu)) {
1242+
} else if (adreno_is_a730(adreno_gpu) || adreno_is_a740(adreno_gpu)) {
11831243
regs = a730_protect;
11841244
count = ARRAY_SIZE(a730_protect);
11851245
count_max = 48;
@@ -1252,7 +1312,8 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
12521312

12531313
if (adreno_is_a650(adreno_gpu) ||
12541314
adreno_is_a660(adreno_gpu) ||
1255-
adreno_is_a730(adreno_gpu)) {
1315+
adreno_is_a730(adreno_gpu) ||
1316+
adreno_is_a740_family(adreno_gpu)) {
12561317
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
12571318
hbb_lo = 3;
12581319
amsbc = 1;
@@ -1545,6 +1606,7 @@ static int hw_init(struct msm_gpu *gpu)
15451606
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
15461607
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
15471608
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1609+
u64 gmem_range_min;
15481610
int ret;
15491611

15501612
if (!adreno_has_gmu_wrapper(adreno_gpu)) {
@@ -1635,11 +1697,13 @@ static int hw_init(struct msm_gpu *gpu)
16351697

16361698
if (!(adreno_is_a650_family(adreno_gpu) ||
16371699
adreno_is_a730(adreno_gpu))) {
1700+
gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M;
1701+
16381702
/* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
1639-
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, 0x00100000);
1703+
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, gmem_range_min);
16401704

16411705
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX,
1642-
0x00100000 + adreno_gpu->info->gmem - 1);
1706+
gmem_range_min + adreno_gpu->info->gmem - 1);
16431707
}
16441708

16451709
if (adreno_is_a7xx(adreno_gpu))
@@ -1704,7 +1768,8 @@ static int hw_init(struct msm_gpu *gpu)
17041768
a6xx_set_ubwc_config(gpu);
17051769

17061770
/* Enable fault detection */
1707-
if (adreno_is_a730(adreno_gpu))
1771+
if (adreno_is_a730(adreno_gpu) ||
1772+
adreno_is_a740_family(adreno_gpu))
17081773
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff);
17091774
else if (adreno_is_a619(adreno_gpu))
17101775
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff);
@@ -2796,7 +2861,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
27962861
!!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
27972862

27982863
/* gpu->info only gets assigned in adreno_gpu_init() */
2799-
is_a7xx = config->info->family == ADRENO_7XX_GEN1;
2864+
is_a7xx = config->info->family == ADRENO_7XX_GEN1 ||
2865+
config->info->family == ADRENO_7XX_GEN2;
28002866

28012867
a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);
28022868

‎drivers/gpu/drm/msm/adreno/a6xx_hfi.c‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -565,6 +565,31 @@ static void a730_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
565565
msg->cnoc_cmds_data[1][0] = 0x60000001;
566566
}
567567

568+
static void a740_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
569+
{
570+
msg->bw_level_num = 1;
571+
572+
msg->ddr_cmds_num = 3;
573+
msg->ddr_wait_bitmask = 0x7;
574+
575+
msg->ddr_cmds_addrs[0] = cmd_db_read_addr("SH0");
576+
msg->ddr_cmds_addrs[1] = cmd_db_read_addr("MC0");
577+
msg->ddr_cmds_addrs[2] = cmd_db_read_addr("ACV");
578+
579+
msg->ddr_cmds_data[0][0] = 0x40000000;
580+
msg->ddr_cmds_data[0][1] = 0x40000000;
581+
msg->ddr_cmds_data[0][2] = 0x40000000;
582+
583+
/* TODO: add a proper dvfs table */
584+
585+
msg->cnoc_cmds_num = 1;
586+
msg->cnoc_wait_bitmask = 0x1;
587+
588+
msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0");
589+
msg->cnoc_cmds_data[0][0] = 0x40000000;
590+
msg->cnoc_cmds_data[1][0] = 0x60000001;
591+
}
592+
568593
static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
569594
{
570595
/* Send a single "off" entry since the 630 GMU doesn't do bus scaling */
@@ -625,6 +650,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
625650
a690_build_bw_table(&msg);
626651
else if (adreno_is_a730(adreno_gpu))
627652
a730_build_bw_table(&msg);
653+
else if (adreno_is_a740_family(adreno_gpu))
654+
a740_build_bw_table(&msg);
628655
else
629656
a6xx_build_bw_table(&msg);
630657

‎drivers/gpu/drm/msm/adreno/adreno_device.c‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -499,10 +499,27 @@ static const struct adreno_info gpulist[] = {
499499
},
500500
.gmem = SZ_2M,
501501
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
502+
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
503+
ADRENO_QUIRK_HAS_HW_APRIV,
502504
.init = a6xx_gpu_init,
503505
.zapfw = "a730_zap.mdt",
504506
.hwcg = a730_hwcg,
505507
.address_space_size = SZ_16G,
508+
}, {
509+
.chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
510+
.family = ADRENO_7XX_GEN2,
511+
.fw = {
512+
[ADRENO_FW_SQE] = "a740_sqe.fw",
513+
[ADRENO_FW_GMU] = "gmu_gen70200.bin",
514+
},
515+
.gmem = 3 * SZ_1M,
516+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
517+
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
518+
ADRENO_QUIRK_HAS_HW_APRIV,
519+
.init = a6xx_gpu_init,
520+
.zapfw = "a740_zap.mdt",
521+
.hwcg = a740_hwcg,
522+
.address_space_size = SZ_16G,
506523
},
507524
};
508525

‎drivers/gpu/drm/msm/adreno/adreno_gpu.c‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -323,7 +323,11 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
323323
*value = adreno_gpu->info->gmem;
324324
return 0;
325325
case MSM_PARAM_GMEM_BASE:
326-
*value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
326+
if (adreno_is_a650_family(adreno_gpu) ||
327+
adreno_is_a740_family(adreno_gpu))
328+
*value = 0;
329+
else
330+
*value = 0x100000;
327331
return 0;
328332
case MSM_PARAM_CHIP_ID:
329333
*value = adreno_gpu->chip_id;

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