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konradybciorobclark
konradybcio
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robclark
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drm/msm/a6xx: Add A730 support
Add support for Adreno 730, also known as GEN7_0_x, found on SM8450. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/559290/ Signed-off-by: Rob Clark <robdclark@chromium.org>
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4 files changed

Lines changed: 203 additions & 4 deletions

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‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 123 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -837,6 +837,63 @@ const struct adreno_reglist a690_hwcg[] = {
837837
{}
838838
};
839839

840+
const struct adreno_reglist a730_hwcg[] = {
841+
{ REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
842+
{ REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
843+
{ REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
844+
{ REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080 },
845+
{ REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222220 },
846+
{ REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
847+
{ REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
848+
{ REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00222222 },
849+
{ REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
850+
{ REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
851+
{ REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
852+
{ REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
853+
{ REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
854+
{ REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
855+
{ REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
856+
{ REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
857+
{ REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
858+
{ REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
859+
{ REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
860+
{ REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
861+
{ REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222 },
862+
{ REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
863+
{ REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x44000f00 },
864+
{ REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022 },
865+
{ REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555 },
866+
{ REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
867+
{ REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00440044 },
868+
{ REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
869+
{ REG_A7XX_RBBM_CLOCK_MODE2_GRAS, 0x00000222 },
870+
{ REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS, 0x00222222 },
871+
{ REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222223 },
872+
{ REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
873+
{ REG_A7XX_RBBM_CLOCK_MODE_BV_GPC, 0x00222222 },
874+
{ REG_A7XX_RBBM_CLOCK_MODE_BV_VFD, 0x00002222 },
875+
{ REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
876+
{ REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
877+
{ REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
878+
{ REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
879+
{ REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
880+
{ REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
881+
{ REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
882+
{ REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
883+
{ REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
884+
{ REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
885+
{ REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ, 0x55555552 },
886+
{ REG_A7XX_RBBM_CLOCK_MODE_CP, 0x00000223 },
887+
{ REG_A6XX_RBBM_CLOCK_CNTL, 0x8aa8aa82 },
888+
{ REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
889+
{ REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
890+
{ REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
891+
{ REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
892+
{ REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
893+
{ REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
894+
{},
895+
};
896+
840897
static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
841898
{
842899
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -1048,6 +1105,59 @@ static const u32 a690_protect[] = {
10481105
A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */
10491106
};
10501107

1108+
static const u32 a730_protect[] = {
1109+
A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
1110+
A6XX_PROTECT_RDONLY(0x0050b, 0x0058),
1111+
A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
1112+
A6XX_PROTECT_NORDWR(0x00510, 0x0000),
1113+
A6XX_PROTECT_NORDWR(0x00534, 0x0000),
1114+
A6XX_PROTECT_RDONLY(0x005fb, 0x009d),
1115+
A6XX_PROTECT_NORDWR(0x00699, 0x01e9),
1116+
A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
1117+
A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
1118+
/* 0x008d0-0x008dd are unprotected on purpose for tools like perfetto */
1119+
A6XX_PROTECT_RDONLY(0x008de, 0x0154),
1120+
A6XX_PROTECT_NORDWR(0x00900, 0x004d),
1121+
A6XX_PROTECT_NORDWR(0x0098d, 0x00b2),
1122+
A6XX_PROTECT_NORDWR(0x00a41, 0x01be),
1123+
A6XX_PROTECT_NORDWR(0x00df0, 0x0001),
1124+
A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1125+
A6XX_PROTECT_NORDWR(0x00e07, 0x0008),
1126+
A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
1127+
A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
1128+
A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
1129+
A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
1130+
A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
1131+
A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
1132+
A6XX_PROTECT_NORDWR(0x08e80, 0x0280),
1133+
A6XX_PROTECT_NORDWR(0x09624, 0x01db),
1134+
A6XX_PROTECT_NORDWR(0x09e40, 0x0000),
1135+
A6XX_PROTECT_NORDWR(0x09e64, 0x000d),
1136+
A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
1137+
A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
1138+
A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
1139+
A6XX_PROTECT_NORDWR(0x0ae50, 0x000f),
1140+
A6XX_PROTECT_NORDWR(0x0ae66, 0x0003),
1141+
A6XX_PROTECT_NORDWR(0x0ae6f, 0x0003),
1142+
A6XX_PROTECT_NORDWR(0x0b604, 0x0003),
1143+
A6XX_PROTECT_NORDWR(0x0ec00, 0x0fff),
1144+
A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1145+
A6XX_PROTECT_NORDWR(0x18400, 0x0053),
1146+
A6XX_PROTECT_RDONLY(0x18454, 0x0004),
1147+
A6XX_PROTECT_NORDWR(0x18459, 0x1fff),
1148+
A6XX_PROTECT_NORDWR(0x1a459, 0x1fff),
1149+
A6XX_PROTECT_NORDWR(0x1c459, 0x1fff),
1150+
A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
1151+
A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
1152+
A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
1153+
A6XX_PROTECT_NORDWR(0x1f878, 0x002a),
1154+
/* CP_PROTECT_REG[44, 46] are left untouched! */
1155+
0,
1156+
0,
1157+
0,
1158+
A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000),
1159+
};
1160+
10511161
static void a6xx_set_cp_protect(struct msm_gpu *gpu)
10521162
{
10531163
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -1069,6 +1179,11 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
10691179
count = ARRAY_SIZE(a660_protect);
10701180
count_max = 48;
10711181
BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48);
1182+
} else if (adreno_is_a730(adreno_gpu)) {
1183+
regs = a730_protect;
1184+
count = ARRAY_SIZE(a730_protect);
1185+
count_max = 48;
1186+
BUILD_BUG_ON(ARRAY_SIZE(a730_protect) > 48);
10721187
} else {
10731188
regs = a6xx_protect;
10741189
count = ARRAY_SIZE(a6xx_protect);
@@ -1135,7 +1250,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
11351250
if (adreno_is_a640_family(adreno_gpu))
11361251
amsbc = 1;
11371252

1138-
if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) {
1253+
if (adreno_is_a650(adreno_gpu) ||
1254+
adreno_is_a660(adreno_gpu) ||
1255+
adreno_is_a730(adreno_gpu)) {
11391256
/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
11401257
hbb_lo = 3;
11411258
amsbc = 1;
@@ -1516,7 +1633,8 @@ static int hw_init(struct msm_gpu *gpu)
15161633
gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu);
15171634
}
15181635

1519-
if (!adreno_is_a650_family(adreno_gpu)) {
1636+
if (!(adreno_is_a650_family(adreno_gpu) ||
1637+
adreno_is_a730(adreno_gpu))) {
15201638
/* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
15211639
gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, 0x00100000);
15221640

@@ -1586,7 +1704,9 @@ static int hw_init(struct msm_gpu *gpu)
15861704
a6xx_set_ubwc_config(gpu);
15871705

15881706
/* Enable fault detection */
1589-
if (adreno_is_a619(adreno_gpu))
1707+
if (adreno_is_a730(adreno_gpu))
1708+
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff);
1709+
else if (adreno_is_a619(adreno_gpu))
15901710
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff);
15911711
else if (adreno_is_a610(adreno_gpu))
15921712
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff);

‎drivers/gpu/drm/msm/adreno/a6xx_hfi.c‎

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@
55
#include <linux/circ_buf.h>
66
#include <linux/list.h>
77

8+
#include <soc/qcom/cmd-db.h>
9+
810
#include "a6xx_gmu.h"
911
#include "a6xx_gmu.xml.h"
1012
#include "a6xx_gpu.h"
@@ -506,6 +508,63 @@ static void adreno_7c3_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
506508
msg->cnoc_cmds_data[0][0] = 0x40000000;
507509
msg->cnoc_cmds_data[1][0] = 0x60000001;
508510
}
511+
512+
static void a730_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
513+
{
514+
msg->bw_level_num = 12;
515+
516+
msg->ddr_cmds_num = 3;
517+
msg->ddr_wait_bitmask = 0x7;
518+
519+
msg->ddr_cmds_addrs[0] = cmd_db_read_addr("SH0");
520+
msg->ddr_cmds_addrs[1] = cmd_db_read_addr("MC0");
521+
msg->ddr_cmds_addrs[2] = cmd_db_read_addr("ACV");
522+
523+
msg->ddr_cmds_data[0][0] = 0x40000000;
524+
msg->ddr_cmds_data[0][1] = 0x40000000;
525+
msg->ddr_cmds_data[0][2] = 0x40000000;
526+
msg->ddr_cmds_data[1][0] = 0x600002e8;
527+
msg->ddr_cmds_data[1][1] = 0x600003d0;
528+
msg->ddr_cmds_data[1][2] = 0x60000008;
529+
msg->ddr_cmds_data[2][0] = 0x6000068d;
530+
msg->ddr_cmds_data[2][1] = 0x6000089a;
531+
msg->ddr_cmds_data[2][2] = 0x60000008;
532+
msg->ddr_cmds_data[3][0] = 0x600007f2;
533+
msg->ddr_cmds_data[3][1] = 0x60000a6e;
534+
msg->ddr_cmds_data[3][2] = 0x60000008;
535+
msg->ddr_cmds_data[4][0] = 0x600009e5;
536+
msg->ddr_cmds_data[4][1] = 0x60000cfd;
537+
msg->ddr_cmds_data[4][2] = 0x60000008;
538+
msg->ddr_cmds_data[5][0] = 0x60000b29;
539+
msg->ddr_cmds_data[5][1] = 0x60000ea6;
540+
msg->ddr_cmds_data[5][2] = 0x60000008;
541+
msg->ddr_cmds_data[6][0] = 0x60001698;
542+
msg->ddr_cmds_data[6][1] = 0x60001da8;
543+
msg->ddr_cmds_data[6][2] = 0x60000008;
544+
msg->ddr_cmds_data[7][0] = 0x600018d2;
545+
msg->ddr_cmds_data[7][1] = 0x60002093;
546+
msg->ddr_cmds_data[7][2] = 0x60000008;
547+
msg->ddr_cmds_data[8][0] = 0x60001e66;
548+
msg->ddr_cmds_data[8][1] = 0x600027e6;
549+
msg->ddr_cmds_data[8][2] = 0x60000008;
550+
msg->ddr_cmds_data[9][0] = 0x600027c2;
551+
msg->ddr_cmds_data[9][1] = 0x6000342f;
552+
msg->ddr_cmds_data[9][2] = 0x60000008;
553+
msg->ddr_cmds_data[10][0] = 0x60002e71;
554+
msg->ddr_cmds_data[10][1] = 0x60003cf5;
555+
msg->ddr_cmds_data[10][2] = 0x60000008;
556+
msg->ddr_cmds_data[11][0] = 0x600030ae;
557+
msg->ddr_cmds_data[11][1] = 0x60003fe5;
558+
msg->ddr_cmds_data[11][2] = 0x60000008;
559+
560+
msg->cnoc_cmds_num = 1;
561+
msg->cnoc_wait_bitmask = 0x1;
562+
563+
msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0");
564+
msg->cnoc_cmds_data[0][0] = 0x40000000;
565+
msg->cnoc_cmds_data[1][0] = 0x60000001;
566+
}
567+
509568
static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
510569
{
511570
/* Send a single "off" entry since the 630 GMU doesn't do bus scaling */
@@ -564,6 +623,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
564623
a660_build_bw_table(&msg);
565624
else if (adreno_is_a690(adreno_gpu))
566625
a690_build_bw_table(&msg);
626+
else if (adreno_is_a730(adreno_gpu))
627+
a730_build_bw_table(&msg);
567628
else
568629
a6xx_build_bw_table(&msg);
569630

‎drivers/gpu/drm/msm/adreno/adreno_device.c‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -490,6 +490,19 @@ static const struct adreno_info gpulist[] = {
490490
.zapfw = "a690_zap.mdt",
491491
.hwcg = a690_hwcg,
492492
.address_space_size = SZ_16G,
493+
}, {
494+
.chip_ids = ADRENO_CHIP_IDS(0x07030001),
495+
.family = ADRENO_7XX_GEN1,
496+
.fw = {
497+
[ADRENO_FW_SQE] = "a730_sqe.fw",
498+
[ADRENO_FW_GMU] = "gmu_gen70000.bin",
499+
},
500+
.gmem = SZ_2M,
501+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
502+
.init = a6xx_gpu_init,
503+
.zapfw = "a730_zap.mdt",
504+
.hwcg = a730_hwcg,
505+
.address_space_size = SZ_16G,
493506
},
494507
};
495508

‎drivers/gpu/drm/msm/adreno/adreno_gpu.h‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@ struct adreno_reglist {
7676
};
7777

7878
extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[];
79-
extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];
79+
extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a730_hwcg[];
8080

8181
struct adreno_speedbin {
8282
uint16_t fuse;
@@ -403,6 +403,11 @@ static inline int adreno_is_a640_family(const struct adreno_gpu *gpu)
403403
return gpu->info->family == ADRENO_6XX_GEN2;
404404
}
405405

406+
static inline int adreno_is_a730(struct adreno_gpu *gpu)
407+
{
408+
return gpu->info->chip_ids[0] == 0x07030001;
409+
}
410+
406411
static inline int adreno_is_a7xx(struct adreno_gpu *gpu)
407412
{
408413
/* Update with non-fake (i.e. non-A702) Gen 7 GPUs */

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