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Merge tag 'riscv-dt-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.19 MAINTAINERS: There's some re-jigging of things to reduce duplication, by moving me into the StarFive entry and my tree into the Microchip one. The other platforms that I look after (SiFive and Canaan) are marked as Odd Fixes to better represent their status. Nothing functionally changes. Microchip: Add adc and mmc nodes for the Beagle-V Fire. SiFive: Add pwm fans to the unmatched board. StarFive: Add the Orange PI RV board, another VisionFive 2 derived SBC. This required moving a mmc related nodes out of the common file, into <board>.dts. Yet more things moved out of the common file when the VisionFive 2 Lite boards were added, which use the JH7110S SoC instead of the JH7110. The difference here between SoCs is just temperature and frequency ranges, but the boards differ enough that the pool of common nodes decreases a little further. There's an eMMC and an SD variant here, that are different SKUs, bringing the total new StarFive boards to three. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: add Orange Pi RV dt-bindings: riscv: starfive: add xunlong,orangepi-rv riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree riscv: dts: starfive: Add VisionFive 2 Lite board device tree riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board MAINTAINERS: degrade RISC-V MISC SOC SUPPORT to Odd Fixes MAINTAINERS: add tree to RISC-V Microchip entry MAINTAINERS: remove patchwork from RISC-V MISC SOC SUPPORT MAINTAINERS: add Conor to StarFive entry riscv: dts: sifive: unmatched: Add PWM controlled fans riscv: dts: microchip: enable qspi adc/mmc-spi-slot on BeagleV Fire dts: starfive: jh7110-common: split out mmc0 reset pins from common into boards Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents ce48af1 + 5b70764 commit 3aa9940

17 files changed

Lines changed: 528 additions & 23 deletions

‎Documentation/devicetree/bindings/riscv/starfive.yaml‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,8 +33,15 @@ properties:
3333
- pine64,star64
3434
- starfive,visionfive-2-v1.2a
3535
- starfive,visionfive-2-v1.3b
36+
- xunlong,orangepi-rv
3637
- const: starfive,jh7110
3738

39+
- items:
40+
- enum:
41+
- starfive,visionfive-2-lite
42+
- starfive,visionfive-2-lite-emmc
43+
- const: starfive,jh7110s
44+
3845
additionalProperties: true
3946

4047
...

‎MAINTAINERS‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22110,6 +22110,7 @@ M: Conor Dooley <conor.dooley@microchip.com>
2211022110
M: Daire McNamara <daire.mcnamara@microchip.com>
2211122111
L: linux-riscv@lists.infradead.org
2211222112
S: Supported
22113+
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ (dts, soc, firmware)
2211322114
F: Documentation/devicetree/bindings/clock/microchip,mpfs*.yaml
2211422115
F: Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
2211522116
F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml
@@ -22140,13 +22141,10 @@ F: include/soc/microchip/mpfs.h
2214022141
RISC-V MISC SOC SUPPORT
2214122142
M: Conor Dooley <conor@kernel.org>
2214222143
L: linux-riscv@lists.infradead.org
22143-
S: Maintained
22144-
Q: https://patchwork.kernel.org/project/linux-riscv/list/
22144+
S: Odd Fixes
2214522145
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
2214622146
F: arch/riscv/boot/dts/canaan/
22147-
F: arch/riscv/boot/dts/microchip/
2214822147
F: arch/riscv/boot/dts/sifive/
22149-
F: arch/riscv/boot/dts/starfive/
2215022148

2215122149
RISC-V PMU DRIVERS
2215222150
M: Atish Patra <atish.patra@linux.dev>
@@ -24471,7 +24469,10 @@ F: drivers/crypto/starfive/
2447124469

2447224470
STARFIVE DEVICETREES
2447324471
M: Emil Renner Berthing <kernel@esmil.dk>
24472+
M: Conor Dooley <conor@kernel.org>
24473+
L: linux-riscv@lists.infradead.org
2447424474
S: Maintained
24475+
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
2447524476
F: arch/riscv/boot/dts/starfive/
2447624477

2447724478
STARFIVE DWMAC GLUE LAYER

‎arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts‎

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,26 @@
7979

8080
};
8181

82+
&gpio0 {
83+
interrupts = <13>, <14>, <15>, <16>,
84+
<17>, <18>, <19>, <20>,
85+
<21>, <22>, <23>, <24>,
86+
<25>, <26>;
87+
ngpios = <14>;
88+
status = "okay";
89+
};
90+
91+
&gpio1 {
92+
interrupts = <27>, <28>, <29>, <30>,
93+
<31>, <32>, <33>, <34>,
94+
<35>, <36>, <37>, <38>,
95+
<39>, <40>, <41>, <42>,
96+
<43>, <44>, <45>, <46>,
97+
<47>, <48>, <49>, <50>;
98+
ngpios = <24>;
99+
status = "okay";
100+
};
101+
82102
&gpio2 {
83103
interrupts = <53>, <53>, <53>, <53>,
84104
<53>, <53>, <53>, <53>,
@@ -199,6 +219,82 @@
199219
status = "okay";
200220
};
201221

222+
&qspi {
223+
status = "okay";
224+
cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>, <&gpio0 12 GPIO_ACTIVE_LOW>;
225+
num-cs = <2>;
226+
227+
adc@0 {
228+
compatible = "microchip,mcp3464r";
229+
reg = <0>; /* CE0 */
230+
spi-cpol;
231+
spi-cpha;
232+
spi-max-frequency = <5000000>;
233+
microchip,hw-device-address = <1>;
234+
#address-cells = <1>;
235+
#size-cells = <0>;
236+
status = "okay";
237+
238+
channel@0 {
239+
/* CH0 to AGND */
240+
reg = <0>;
241+
label = "CH0";
242+
};
243+
244+
channel@1 {
245+
/* CH1 to AGND */
246+
reg = <1>;
247+
label = "CH1";
248+
};
249+
250+
channel@2 {
251+
/* CH2 to AGND */
252+
reg = <2>;
253+
label = "CH2";
254+
};
255+
256+
channel@3 {
257+
/* CH3 to AGND */
258+
reg = <3>;
259+
label = "CH3";
260+
};
261+
262+
channel@4 {
263+
/* CH4 to AGND */
264+
reg = <4>;
265+
label = "CH4";
266+
};
267+
268+
channel@5 {
269+
/* CH5 to AGND */
270+
reg = <5>;
271+
label = "CH5";
272+
};
273+
274+
channel@6 {
275+
/* CH6 to AGND */
276+
reg = <6>;
277+
label = "CH6";
278+
};
279+
280+
channel@7 {
281+
/* CH7 is connected to AGND */
282+
reg = <7>;
283+
label = "CH7";
284+
};
285+
};
286+
287+
mmc@1 {
288+
compatible = "mmc-spi-slot";
289+
reg = <1>;
290+
gpios = <&gpio2 31 1>;
291+
voltage-ranges = <3300 3300>;
292+
spi-max-frequency = <5000000>;
293+
disable-wp;
294+
};
295+
};
296+
297+
202298
&syscontroller {
203299
microchip,bitstream-flash = <&sys_ctrl_flash>;
204300
status = "okay";

‎arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts‎

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Original file line numberDiff line numberDiff line change
@@ -47,6 +47,16 @@
4747
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
4848
};
4949

50+
fan1 {
51+
compatible = "pwm-fan";
52+
pwms = <&pwm1 2 7812500 0>;
53+
};
54+
55+
fan2 {
56+
compatible = "pwm-fan";
57+
pwms = <&pwm1 3 7812500 0>;
58+
};
59+
5060
led-controller-1 {
5161
compatible = "pwm-leds";
5262

‎arch/riscv/boot/dts/starfive/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -12,6 +12,9 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-deepcomputing-fml13v01.dtb
1212
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
1313
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-emmc.dtb
1414
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-lite.dtb
15+
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-orangepi-rv.dtb
1516
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
17+
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
18+
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
1619
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
1720
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb

‎arch/riscv/boot/dts/starfive/jh7110-common.dtsi‎

Lines changed: 0 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -281,14 +281,8 @@
281281
assigned-clock-rates = <50000000>;
282282
bus-width = <8>;
283283
bootph-pre-ram;
284-
cap-mmc-highspeed;
285-
mmc-ddr-1_8v;
286-
mmc-hs200-1_8v;
287-
cap-mmc-hw-reset;
288284
pinctrl-names = "default";
289285
pinctrl-0 = <&mmc0_pins>;
290-
vmmc-supply = <&vcc_3v3>;
291-
vqmmc-supply = <&emmc_vdd>;
292286
status = "okay";
293287
};
294288

@@ -298,8 +292,6 @@
298292
assigned-clock-rates = <50000000>;
299293
bus-width = <4>;
300294
bootph-pre-ram;
301-
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
302-
disable-wp;
303295
cap-sd-highspeed;
304296
pinctrl-names = "default";
305297
pinctrl-0 = <&mmc1_pins>;
@@ -444,17 +436,6 @@
444436
};
445437

446438
mmc0_pins: mmc0-0 {
447-
rst-pins {
448-
pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
449-
GPOEN_ENABLE,
450-
GPI_NONE)>;
451-
bias-pull-up;
452-
drive-strength = <12>;
453-
input-disable;
454-
input-schmitt-disable;
455-
slew-rate = <0>;
456-
};
457-
458439
mmc-pins {
459440
pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
460441
<PINMUX(PAD_SD0_CMD, 0)>,

‎arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts‎

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Original file line numberDiff line numberDiff line change
@@ -11,6 +11,33 @@
1111
compatible = "deepcomputing,fml13v01", "starfive,jh7110";
1212
};
1313

14+
&mmc0 {
15+
cap-mmc-highspeed;
16+
cap-mmc-hw-reset;
17+
mmc-ddr-1_8v;
18+
mmc-hs200-1_8v;
19+
vmmc-supply = <&vcc_3v3>;
20+
vqmmc-supply = <&emmc_vdd>;
21+
};
22+
23+
&mmc0_pins {
24+
rst-pins {
25+
pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
26+
GPOEN_ENABLE,
27+
GPI_NONE)>;
28+
bias-pull-up;
29+
drive-strength = <12>;
30+
input-disable;
31+
input-schmitt-disable;
32+
slew-rate = <0>;
33+
};
34+
};
35+
36+
&mmc1 {
37+
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
38+
disable-wp;
39+
};
40+
1441
&pcie1 {
1542
perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
1643
phys = <&pciephy1>;

‎arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts‎

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Original file line numberDiff line numberDiff line change
@@ -22,6 +22,33 @@
2222
status = "okay";
2323
};
2424

25+
&mmc0 {
26+
cap-mmc-highspeed;
27+
cap-mmc-hw-reset;
28+
mmc-ddr-1_8v;
29+
mmc-hs200-1_8v;
30+
vmmc-supply = <&vcc_3v3>;
31+
vqmmc-supply = <&emmc_vdd>;
32+
};
33+
34+
&mmc0_pins {
35+
rst-pins {
36+
pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
37+
GPOEN_ENABLE,
38+
GPI_NONE)>;
39+
bias-pull-up;
40+
drive-strength = <12>;
41+
input-disable;
42+
input-schmitt-disable;
43+
slew-rate = <0>;
44+
};
45+
};
46+
47+
&mmc1 {
48+
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
49+
disable-wp;
50+
};
51+
2552
&pcie0 {
2653
status = "okay";
2754
};

‎arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,3 +10,12 @@
1010
model = "Milk-V Mars CM";
1111
compatible = "milkv,marscm-emmc", "starfive,jh7110";
1212
};
13+
14+
&mmc0 {
15+
cap-mmc-highspeed;
16+
cap-mmc-hw-reset;
17+
mmc-ddr-1_8v;
18+
mmc-hs200-1_8v;
19+
vmmc-supply = <&vcc_3v3>;
20+
vqmmc-supply = <&emmc_vdd>;
21+
};

‎arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts‎

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Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
&mmc0 {
1515
bus-width = <4>;
1616
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
17+
disable-wp;
1718
};
1819

1920
&mmc0_pins {

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