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konradybcioGeorgi Djakov
konradybcio
authored and
Georgi Djakov
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interconnect: qcom: sdm670: Retire DEFINE_QBCM
The struct definition macros are hard to read and compare, expand them. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-12-c03aaeffc769@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
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Lines changed: 215 additions & 24 deletions

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‎drivers/interconnect/qcom/sdm670.c‎

Lines changed: 215 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1045,30 +1045,221 @@ static struct qcom_icc_node xs_sys_tcu_cfg = {
10451045
.buswidth = 8,
10461046
};
10471047

1048-
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
1049-
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
1050-
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
1051-
DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
1052-
DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io);
1053-
DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1);
1054-
DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc);
1055-
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc);
1056-
DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu);
1057-
DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9);
1058-
DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps);
1059-
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf);
1060-
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
1061-
DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emmc_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
1062-
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2);
1063-
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
1064-
DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc);
1065-
DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc);
1066-
DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem, &qxs_pimem);
1067-
DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm);
1068-
DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre1_noc, &srvc_aggre1_noc);
1069-
DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_aggre2_noc, &srvc_aggre2_noc);
1070-
DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gladiator_sodv, &xm_gic);
1071-
DEFINE_QBCM(bcm_sn13, "SN13", false, &qnm_memnoc);
1048+
static struct qcom_icc_bcm bcm_acv = {
1049+
.name = "ACV",
1050+
.keepalive = false,
1051+
.num_nodes = 1,
1052+
.nodes = { &ebi },
1053+
};
1054+
1055+
static struct qcom_icc_bcm bcm_mc0 = {
1056+
.name = "MC0",
1057+
.keepalive = true,
1058+
.num_nodes = 1,
1059+
.nodes = { &ebi },
1060+
};
1061+
1062+
static struct qcom_icc_bcm bcm_sh0 = {
1063+
.name = "SH0",
1064+
.keepalive = true,
1065+
.num_nodes = 1,
1066+
.nodes = { &qns_llcc },
1067+
};
1068+
1069+
static struct qcom_icc_bcm bcm_mm0 = {
1070+
.name = "MM0",
1071+
.keepalive = true,
1072+
.num_nodes = 1,
1073+
.nodes = { &qns_mem_noc_hf },
1074+
};
1075+
1076+
static struct qcom_icc_bcm bcm_sh1 = {
1077+
.name = "SH1",
1078+
.keepalive = false,
1079+
.num_nodes = 1,
1080+
.nodes = { &qns_apps_io },
1081+
};
1082+
1083+
static struct qcom_icc_bcm bcm_mm1 = {
1084+
.name = "MM1",
1085+
.keepalive = true,
1086+
.num_nodes = 7,
1087+
.nodes = { &qxm_camnoc_hf0_uncomp,
1088+
&qxm_camnoc_hf1_uncomp,
1089+
&qxm_camnoc_sf_uncomp,
1090+
&qxm_camnoc_hf0,
1091+
&qxm_camnoc_hf1,
1092+
&qxm_mdp0,
1093+
&qxm_mdp1
1094+
},
1095+
};
1096+
1097+
static struct qcom_icc_bcm bcm_sh2 = {
1098+
.name = "SH2",
1099+
.keepalive = false,
1100+
.num_nodes = 1,
1101+
.nodes = { &qns_memnoc_snoc },
1102+
};
1103+
1104+
static struct qcom_icc_bcm bcm_mm2 = {
1105+
.name = "MM2",
1106+
.keepalive = false,
1107+
.num_nodes = 1,
1108+
.nodes = { &qns2_mem_noc },
1109+
};
1110+
1111+
static struct qcom_icc_bcm bcm_sh3 = {
1112+
.name = "SH3",
1113+
.keepalive = false,
1114+
.num_nodes = 1,
1115+
.nodes = { &acm_tcu },
1116+
};
1117+
1118+
static struct qcom_icc_bcm bcm_mm3 = {
1119+
.name = "MM3",
1120+
.keepalive = false,
1121+
.num_nodes = 5,
1122+
.nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 },
1123+
};
1124+
1125+
static struct qcom_icc_bcm bcm_sh5 = {
1126+
.name = "SH5",
1127+
.keepalive = false,
1128+
.num_nodes = 1,
1129+
.nodes = { &qnm_apps },
1130+
};
1131+
1132+
static struct qcom_icc_bcm bcm_sn0 = {
1133+
.name = "SN0",
1134+
.keepalive = true,
1135+
.num_nodes = 1,
1136+
.nodes = { &qns_memnoc_sf },
1137+
};
1138+
1139+
static struct qcom_icc_bcm bcm_ce0 = {
1140+
.name = "CE0",
1141+
.keepalive = false,
1142+
.num_nodes = 1,
1143+
.nodes = { &qxm_crypto },
1144+
};
1145+
1146+
static struct qcom_icc_bcm bcm_cn0 = {
1147+
.name = "CN0",
1148+
.keepalive = true,
1149+
.num_nodes = 41,
1150+
.nodes = { &qhm_spdm,
1151+
&qnm_snoc,
1152+
&qhs_a1_noc_cfg,
1153+
&qhs_a2_noc_cfg,
1154+
&qhs_aop,
1155+
&qhs_aoss,
1156+
&qhs_camera_cfg,
1157+
&qhs_clk_ctl,
1158+
&qhs_compute_dsp_cfg,
1159+
&qhs_cpr_cx,
1160+
&qhs_crypto0_cfg,
1161+
&qhs_dcc_cfg,
1162+
&qhs_ddrss_cfg,
1163+
&qhs_display_cfg,
1164+
&qhs_emmc_cfg,
1165+
&qhs_glm,
1166+
&qhs_gpuss_cfg,
1167+
&qhs_imem_cfg,
1168+
&qhs_ipa,
1169+
&qhs_mnoc_cfg,
1170+
&qhs_pdm,
1171+
&qhs_phy_refgen_south,
1172+
&qhs_pimem_cfg,
1173+
&qhs_prng,
1174+
&qhs_qdss_cfg,
1175+
&qhs_qupv3_north,
1176+
&qhs_qupv3_south,
1177+
&qhs_sdc2,
1178+
&qhs_sdc4,
1179+
&qhs_snoc_cfg,
1180+
&qhs_spdm,
1181+
&qhs_tcsr,
1182+
&qhs_tlmm_north,
1183+
&qhs_tlmm_south,
1184+
&qhs_tsif,
1185+
&qhs_ufs_mem_cfg,
1186+
&qhs_usb3_0,
1187+
&qhs_venus_cfg,
1188+
&qhs_vsense_ctrl_cfg,
1189+
&qns_cnoc_a2noc,
1190+
&srvc_cnoc
1191+
},
1192+
};
1193+
1194+
static struct qcom_icc_bcm bcm_qup0 = {
1195+
.name = "QUP0",
1196+
.keepalive = false,
1197+
.num_nodes = 2,
1198+
.nodes = { &qhm_qup1, &qhm_qup2 },
1199+
};
1200+
1201+
static struct qcom_icc_bcm bcm_sn1 = {
1202+
.name = "SN1",
1203+
.keepalive = false,
1204+
.num_nodes = 1,
1205+
.nodes = { &qxs_imem },
1206+
};
1207+
1208+
static struct qcom_icc_bcm bcm_sn2 = {
1209+
.name = "SN2",
1210+
.keepalive = false,
1211+
.num_nodes = 1,
1212+
.nodes = { &qns_memnoc_gc },
1213+
};
1214+
1215+
static struct qcom_icc_bcm bcm_sn3 = {
1216+
.name = "SN3",
1217+
.keepalive = false,
1218+
.num_nodes = 1,
1219+
.nodes = { &qns_cnoc },
1220+
};
1221+
1222+
static struct qcom_icc_bcm bcm_sn4 = {
1223+
.name = "SN4",
1224+
.keepalive = false,
1225+
.num_nodes = 2,
1226+
.nodes = { &qxm_pimem, &qxs_pimem },
1227+
};
1228+
1229+
static struct qcom_icc_bcm bcm_sn5 = {
1230+
.name = "SN5",
1231+
.keepalive = false,
1232+
.num_nodes = 1,
1233+
.nodes = { &xs_qdss_stm },
1234+
};
1235+
1236+
static struct qcom_icc_bcm bcm_sn8 = {
1237+
.name = "SN8",
1238+
.keepalive = false,
1239+
.num_nodes = 2,
1240+
.nodes = { &qnm_aggre1_noc, &srvc_aggre1_noc },
1241+
};
1242+
1243+
static struct qcom_icc_bcm bcm_sn10 = {
1244+
.name = "SN10",
1245+
.keepalive = false,
1246+
.num_nodes = 2,
1247+
.nodes = { &qnm_aggre2_noc, &srvc_aggre2_noc },
1248+
};
1249+
1250+
static struct qcom_icc_bcm bcm_sn11 = {
1251+
.name = "SN11",
1252+
.keepalive = false,
1253+
.num_nodes = 2,
1254+
.nodes = { &qnm_gladiator_sodv, &xm_gic },
1255+
};
1256+
1257+
static struct qcom_icc_bcm bcm_sn13 = {
1258+
.name = "SN13",
1259+
.keepalive = false,
1260+
.num_nodes = 1,
1261+
.nodes = { &qnm_memnoc },
1262+
};
10721263

10731264
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
10741265
&bcm_qup0,

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