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anderssonandersson
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Merge branch '20251003-topic-hamoa_gcc_usb4-v2-1-61d27a14ee65@oss.qualcomm.com' into clk-for-6.19
Merge the addition of missing USB4 clocks and resets in the Hamoa global clock controller binding, to allow sharing them with the DeviceTree branch.
2 parents 3a86608 + e4c4f5a commit 49551c7

2 files changed

Lines changed: 119 additions & 4 deletions

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‎Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml‎

Lines changed: 58 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,9 +32,36 @@ properties:
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- description: PCIe 5 pipe clock
3333
- description: PCIe 6a pipe clock
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- description: PCIe 6b pipe clock
35-
- description: USB QMP Phy 0 clock source
36-
- description: USB QMP Phy 1 clock source
37-
- description: USB QMP Phy 2 clock source
35+
- description: USB4_0 QMPPHY clock source
36+
- description: USB4_1 QMPPHY clock source
37+
- description: USB4_2 QMPPHY clock source
38+
- description: USB4_0 PHY DP0 GMUX clock source
39+
- description: USB4_0 PHY DP1 GMUX clock source
40+
- description: USB4_0 PHY PCIE PIPEGMUX clock source
41+
- description: USB4_0 PHY PIPEGMUX clock source
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- description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
43+
- description: USB4_1 PHY DP0 GMUX 2 clock source
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- description: USB4_1 PHY DP1 GMUX 2 clock source
45+
- description: USB4_1 PHY PCIE PIPEGMUX clock source
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- description: USB4_1 PHY PIPEGMUX clock source
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- description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
48+
- description: USB4_2 PHY DP0 GMUX 2 clock source
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- description: USB4_2 PHY DP1 GMUX 2 clock source
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- description: USB4_2 PHY PCIE PIPEGMUX clock source
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- description: USB4_2 PHY PIPEGMUX clock source
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- description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
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- description: USB4_0 PHY RX 0 clock source
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- description: USB4_0 PHY RX 1 clock source
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- description: USB4_1 PHY RX 0 clock source
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- description: USB4_1 PHY RX 1 clock source
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- description: USB4_2 PHY RX 0 clock source
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- description: USB4_2 PHY RX 1 clock source
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- description: USB4_0 PHY PCIE PIPE clock source
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- description: USB4_0 PHY max PIPE clock source
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- description: USB4_1 PHY PCIE PIPE clock source
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- description: USB4_1 PHY max PIPE clock source
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- description: USB4_2 PHY PCIE PIPE clock source
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- description: USB4_2 PHY max PIPE clock source
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power-domains:
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description:
@@ -67,7 +94,34 @@ examples:
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<&pcie6b_phy>,
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<&usb_1_ss0_qmpphy 0>,
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<&usb_1_ss1_qmpphy 1>,
70-
<&usb_1_ss2_qmpphy 2>;
97+
<&usb_1_ss2_qmpphy 2>,
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<&usb4_0_phy_dp0_gmux_clk>,
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<&usb4_0_phy_dp1_gmux_clk>,
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<&usb4_0_phy_pcie_pipegmux_clk>,
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<&usb4_0_phy_pipegmux_clk>,
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<&usb4_0_phy_sys_pcie_pipegmux_clk>,
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<&usb4_1_phy_dp0_gmux_2_clk>,
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<&usb4_1_phy_dp1_gmux_2_clk>,
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<&usb4_1_phy_pcie_pipegmux_clk>,
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<&usb4_1_phy_pipegmux_clk>,
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<&usb4_1_phy_sys_pcie_pipegmux_clk>,
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<&usb4_2_phy_dp0_gmux_2_clk>,
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<&usb4_2_phy_dp1_gmux_2_clk>,
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<&usb4_2_phy_pcie_pipegmux_clk>,
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<&usb4_2_phy_pipegmux_clk>,
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<&usb4_2_phy_sys_pcie_pipegmux_clk>,
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<&usb4_0_phy_rx_0_clk>,
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<&usb4_0_phy_rx_1_clk>,
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<&usb4_1_phy_rx_0_clk>,
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<&usb4_1_phy_rx_1_clk>,
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<&usb4_2_phy_rx_0_clk>,
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<&usb4_2_phy_rx_1_clk>,
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<&usb4_0_phy_pcie_pipe_clk>,
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<&usb4_0_phy_max_pipe_clk>,
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<&usb4_1_phy_pcie_pipe_clk>,
122+
<&usb4_1_phy_max_pipe_clk>,
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<&usb4_2_phy_pcie_pipe_clk>,
124+
<&usb4_2_phy_max_pipe_clk>;
71125
power-domains = <&rpmhpd RPMHPD_CX>;
72126
#clock-cells = <1>;
73127
#reset-cells = <1>;

‎include/dt-bindings/clock/qcom,x1e80100-gcc.h‎

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -363,6 +363,30 @@
363363
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353
364364
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354
365365
#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355
366+
#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 356
367+
#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 357
368+
#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC 358
369+
#define GCC_USB4_0_PHY_DP0_CLK_SRC 359
370+
#define GCC_USB4_0_PHY_DP1_CLK_SRC 360
371+
#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC 361
372+
#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC 362
373+
#define GCC_USB4_0_PHY_RX0_CLK_SRC 363
374+
#define GCC_USB4_0_PHY_RX1_CLK_SRC 364
375+
#define GCC_USB4_0_PHY_SYS_CLK_SRC 365
376+
#define GCC_USB4_1_PHY_DP0_CLK_SRC 366
377+
#define GCC_USB4_1_PHY_DP1_CLK_SRC 367
378+
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 368
379+
#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 369
380+
#define GCC_USB4_1_PHY_RX0_CLK_SRC 370
381+
#define GCC_USB4_1_PHY_RX1_CLK_SRC 371
382+
#define GCC_USB4_1_PHY_SYS_CLK_SRC 372
383+
#define GCC_USB4_2_PHY_DP0_CLK_SRC 373
384+
#define GCC_USB4_2_PHY_DP1_CLK_SRC 374
385+
#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC 375
386+
#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC 376
387+
#define GCC_USB4_2_PHY_RX0_CLK_SRC 377
388+
#define GCC_USB4_2_PHY_RX1_CLK_SRC 378
389+
#define GCC_USB4_2_PHY_SYS_CLK_SRC 379
366390

367391
/* GCC power domains */
368392
#define GCC_PCIE_0_TUNNEL_GDSC 0
@@ -484,4 +508,41 @@
484508
#define GCC_VIDEO_BCR 87
485509
#define GCC_VIDEO_AXI0_CLK_ARES 88
486510
#define GCC_VIDEO_AXI1_CLK_ARES 89
511+
#define GCC_USB4_0_MISC_USB4_SYS_BCR 90
512+
#define GCC_USB4_0_MISC_RX_CLK_0_BCR 91
513+
#define GCC_USB4_0_MISC_RX_CLK_1_BCR 92
514+
#define GCC_USB4_0_MISC_USB_PIPE_BCR 93
515+
#define GCC_USB4_0_MISC_PCIE_PIPE_BCR 94
516+
#define GCC_USB4_0_MISC_TMU_BCR 95
517+
#define GCC_USB4_0_MISC_SB_IF_BCR 96
518+
#define GCC_USB4_0_MISC_HIA_MSTR_BCR 97
519+
#define GCC_USB4_0_MISC_AHB_BCR 98
520+
#define GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR 99
521+
#define GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR 100
522+
#define GCC_USB4_1_MISC_USB4_SYS_BCR 101
523+
#define GCC_USB4_1_MISC_RX_CLK_0_BCR 102
524+
#define GCC_USB4_1_MISC_RX_CLK_1_BCR 103
525+
#define GCC_USB4_1_MISC_USB_PIPE_BCR 104
526+
#define GCC_USB4_1_MISC_PCIE_PIPE_BCR 105
527+
#define GCC_USB4_1_MISC_TMU_BCR 106
528+
#define GCC_USB4_1_MISC_SB_IF_BCR 107
529+
#define GCC_USB4_1_MISC_HIA_MSTR_BCR 108
530+
#define GCC_USB4_1_MISC_AHB_BCR 109
531+
#define GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR 110
532+
#define GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR 111
533+
#define GCC_USB4_2_MISC_USB4_SYS_BCR 112
534+
#define GCC_USB4_2_MISC_RX_CLK_0_BCR 113
535+
#define GCC_USB4_2_MISC_RX_CLK_1_BCR 114
536+
#define GCC_USB4_2_MISC_USB_PIPE_BCR 115
537+
#define GCC_USB4_2_MISC_PCIE_PIPE_BCR 116
538+
#define GCC_USB4_2_MISC_TMU_BCR 117
539+
#define GCC_USB4_2_MISC_SB_IF_BCR 118
540+
#define GCC_USB4_2_MISC_HIA_MSTR_BCR 119
541+
#define GCC_USB4_2_MISC_AHB_BCR 120
542+
#define GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR 121
543+
#define GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR 122
544+
#define GCC_USB4PHY_PHY_PRIM_BCR 123
545+
#define GCC_USB4PHY_PHY_SEC_BCR 124
546+
#define GCC_USB4PHY_PHY_TERT_BCR 125
547+
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#endif

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