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clocksource/drivers/timer-ti-dm: Simplify register writes with dmtimer_write()
We can simplify register write access by checking for the register write posted mode in the write function. This way we can combine the functions for __omap_dm_timer_write() and omap_dm_timer_write_reg() into a single function dmtimer_write(). We update the shared register access first, the timer revision specific register access will be updated in a later patch. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-4-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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1 file changed

Lines changed: 44 additions & 54 deletions

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‎drivers/clocksource/timer-ti-dm.c‎

Lines changed: 44 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -68,14 +68,29 @@ static inline u32 dmtimer_read(struct omap_dm_timer *timer, u32 reg)
6868
return readl_relaxed(timer->func_base + offset);
6969
}
7070

71-
static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
72-
u32 reg, u32 val, int posted)
71+
/**
72+
* dmtimer_write - write timer registers in posted and non-posted mode
73+
* @timer: timer pointer over which write operation is to perform
74+
* @reg: lowest byte holds the register offset
75+
* @value: data to write into the register
76+
*
77+
* The posted mode bit is encoded in reg. Note that in posted mode, the write
78+
* pending bit must be checked. Otherwise a write on a register which has a
79+
* pending write will be lost.
80+
*/
81+
static inline void dmtimer_write(struct omap_dm_timer *timer, u32 reg, u32 val)
7382
{
74-
if (posted)
75-
while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
83+
u16 wp, offset;
84+
85+
wp = reg >> WPSHIFT;
86+
offset = reg & 0xff;
87+
88+
/* Wait for a possible write pending bit in posted mode */
89+
if (wp && timer->posted)
90+
while (readl_relaxed(timer->pend) & wp)
7691
cpu_relax();
7792

78-
writel_relaxed(val, timer->func_base + (reg & 0xff));
93+
writel_relaxed(val, timer->func_base + offset);
7994
}
8095

8196
static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
@@ -120,25 +135,24 @@ static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
120135

121136
if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
122137
timer->posted = OMAP_TIMER_NONPOSTED;
123-
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
138+
dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0);
124139
return;
125140
}
126141

127-
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
128-
OMAP_TIMER_CTRL_POSTED, 0);
142+
dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED);
129143
timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
130144
timer->posted = OMAP_TIMER_POSTED;
131145
}
132146

133147
static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
134-
int posted, unsigned long rate)
148+
unsigned long rate)
135149
{
136150
u32 l;
137151

138152
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
139153
if (l & OMAP_TIMER_CTRL_ST) {
140154
l &= ~0x1;
141-
__omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
155+
dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
142156
#ifdef CONFIG_ARCH_OMAP2PLUS
143157
/* Readback to make sure write has completed */
144158
dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
@@ -158,7 +172,7 @@ static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
158172
unsigned int value)
159173
{
160174
writel_relaxed(value, timer->irq_ena);
161-
__omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
175+
dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
162176
}
163177

164178
static inline unsigned int
@@ -173,41 +187,17 @@ static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
173187
writel_relaxed(value, timer->irq_stat);
174188
}
175189

176-
/**
177-
* omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
178-
* @timer: timer pointer over which write operation is to perform
179-
* @reg: lowest byte holds the register offset
180-
* @value: data to write into the register
181-
*
182-
* The posted mode bit is encoded in reg. Note that in posted mode the write
183-
* pending bit must be checked. Otherwise a write on a register which has a
184-
* pending write will be lost.
185-
*/
186-
static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
187-
u32 value)
188-
{
189-
WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
190-
__omap_dm_timer_write(timer, reg, value, timer->posted);
191-
}
192-
193190
static void omap_timer_restore_context(struct omap_dm_timer *timer)
194191
{
195-
__omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET,
196-
timer->context.ocp_cfg, 0);
197-
198-
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
199-
timer->context.twer);
200-
omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
201-
timer->context.tcrr);
202-
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
203-
timer->context.tldr);
204-
omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
205-
timer->context.tmar);
206-
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
207-
timer->context.tsicr);
192+
dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg);
193+
194+
dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer);
195+
dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, timer->context.tcrr);
196+
dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr);
197+
dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar);
198+
dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr);
208199
writel_relaxed(timer->context.tier, timer->irq_ena);
209-
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
210-
timer->context.tclr);
200+
dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr);
211201
}
212202

213203
static void omap_timer_save_context(struct omap_dm_timer *timer)
@@ -256,7 +246,7 @@ static int omap_dm_timer_reset(struct omap_dm_timer *timer)
256246
if (timer->revision != 1)
257247
return -EINVAL;
258248

259-
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
249+
dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
260250

261251
do {
262252
l = dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET);
@@ -270,7 +260,7 @@ static int omap_dm_timer_reset(struct omap_dm_timer *timer)
270260
/* Configure timer for smart-idle mode */
271261
l = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET);
272262
l |= 0x2 << 0x3;
273-
__omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
263+
dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l);
274264

275265
timer->posted = 0;
276266

@@ -586,7 +576,7 @@ static int omap_dm_timer_start(struct omap_dm_timer *timer)
586576
l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG);
587577
if (!(l & OMAP_TIMER_CTRL_ST)) {
588578
l |= OMAP_TIMER_CTRL_ST;
589-
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
579+
dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
590580
}
591581

592582
return 0;
@@ -602,7 +592,7 @@ static int omap_dm_timer_stop(struct omap_dm_timer *timer)
602592
if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
603593
rate = clk_get_rate(timer->fclk);
604594

605-
__omap_dm_timer_stop(timer, timer->posted, rate);
595+
__omap_dm_timer_stop(timer, rate);
606596

607597
omap_dm_timer_disable(timer);
608598
return 0;
@@ -615,7 +605,7 @@ static int omap_dm_timer_set_load(struct omap_dm_timer *timer,
615605
return -EINVAL;
616606

617607
omap_dm_timer_enable(timer);
618-
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
608+
dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load);
619609

620610
omap_dm_timer_disable(timer);
621611
return 0;
@@ -635,8 +625,8 @@ static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
635625
l |= OMAP_TIMER_CTRL_CE;
636626
else
637627
l &= ~OMAP_TIMER_CTRL_CE;
638-
omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
639-
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
628+
dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match);
629+
dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
640630

641631
omap_dm_timer_disable(timer);
642632
return 0;
@@ -661,7 +651,7 @@ static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
661651
l |= trigger << 10;
662652
if (autoreload)
663653
l |= OMAP_TIMER_CTRL_AR;
664-
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
654+
dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
665655

666656
omap_dm_timer_disable(timer);
667657
return 0;
@@ -696,7 +686,7 @@ static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
696686
l |= OMAP_TIMER_CTRL_PRE;
697687
l |= prescaler << 2;
698688
}
699-
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
689+
dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l);
700690

701691
omap_dm_timer_disable(timer);
702692
return 0;
@@ -736,7 +726,7 @@ static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
736726

737727
writel_relaxed(l, timer->irq_dis);
738728
l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
739-
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
729+
dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
740730

741731
omap_dm_timer_disable(timer);
742732
return 0;
@@ -783,7 +773,7 @@ static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int
783773
return -EINVAL;
784774
}
785775

786-
omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
776+
dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value);
787777

788778
/* Save the context */
789779
timer->context.tcrr = value;

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