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Linus WalleijRussell King (Oracle)
Linus Walleij
authored and
Russell King (Oracle)
committed
ARM: 9388/2: mm: Type-annotate all per-processor assembly routines
Type tag the remaining per-processor assembly using the CFI symbol macros, in addition to those that were previously tagged for cache maintenance calls. This will be used to finally provide proper C prototypes for all these calls as well so that CFI can be made to work. Tested-by: Kees Cook <keescook@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Sami Tolvanen <samitolvanen@google.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
1 parent b4d20ef commit 51db13a

26 files changed

Lines changed: 434 additions & 274 deletions

‎arch/arm/mm/proc-arm1020.S‎

Lines changed: 15 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -57,18 +57,20 @@
5757
/*
5858
* cpu_arm1020_proc_init()
5959
*/
60-
ENTRY(cpu_arm1020_proc_init)
60+
SYM_TYPED_FUNC_START(cpu_arm1020_proc_init)
6161
ret lr
62+
SYM_FUNC_END(cpu_arm1020_proc_init)
6263

6364
/*
6465
* cpu_arm1020_proc_fin()
6566
*/
66-
ENTRY(cpu_arm1020_proc_fin)
67+
SYM_TYPED_FUNC_START(cpu_arm1020_proc_fin)
6768
mrc p15, 0, r0, c1, c0, 0 @ ctrl register
6869
bic r0, r0, #0x1000 @ ...i............
6970
bic r0, r0, #0x000e @ ............wca.
7071
mcr p15, 0, r0, c1, c0, 0 @ disable caches
7172
ret lr
73+
SYM_FUNC_END(cpu_arm1020_proc_fin)
7274

7375
/*
7476
* cpu_arm1020_reset(loc)
@@ -81,7 +83,7 @@ ENTRY(cpu_arm1020_proc_fin)
8183
*/
8284
.align 5
8385
.pushsection .idmap.text, "ax"
84-
ENTRY(cpu_arm1020_reset)
86+
SYM_TYPED_FUNC_START(cpu_arm1020_reset)
8587
mov ip, #0
8688
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
8789
mcr p15, 0, ip, c7, c10, 4 @ drain WB
@@ -93,16 +95,17 @@ ENTRY(cpu_arm1020_reset)
9395
bic ip, ip, #0x1100 @ ...i...s........
9496
mcr p15, 0, ip, c1, c0, 0 @ ctrl register
9597
ret r0
96-
ENDPROC(cpu_arm1020_reset)
98+
SYM_FUNC_END(cpu_arm1020_reset)
9799
.popsection
98100

99101
/*
100102
* cpu_arm1020_do_idle()
101103
*/
102104
.align 5
103-
ENTRY(cpu_arm1020_do_idle)
105+
SYM_TYPED_FUNC_START(cpu_arm1020_do_idle)
104106
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
105107
ret lr
108+
SYM_FUNC_END(cpu_arm1020_do_idle)
106109

107110
/* ================================= CACHE ================================ */
108111

@@ -360,7 +363,7 @@ SYM_TYPED_FUNC_START(arm1020_dma_unmap_area)
360363
SYM_FUNC_END(arm1020_dma_unmap_area)
361364

362365
.align 5
363-
ENTRY(cpu_arm1020_dcache_clean_area)
366+
SYM_TYPED_FUNC_START(cpu_arm1020_dcache_clean_area)
364367
#ifndef CONFIG_CPU_DCACHE_DISABLE
365368
mov ip, #0
366369
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -370,6 +373,7 @@ ENTRY(cpu_arm1020_dcache_clean_area)
370373
bhi 1b
371374
#endif
372375
ret lr
376+
SYM_FUNC_END(cpu_arm1020_dcache_clean_area)
373377

374378
/* =============================== PageTable ============================== */
375379

@@ -381,7 +385,7 @@ ENTRY(cpu_arm1020_dcache_clean_area)
381385
* pgd: new page tables
382386
*/
383387
.align 5
384-
ENTRY(cpu_arm1020_switch_mm)
388+
SYM_TYPED_FUNC_START(cpu_arm1020_switch_mm)
385389
#ifdef CONFIG_MMU
386390
#ifndef CONFIG_CPU_DCACHE_DISABLE
387391
mcr p15, 0, r3, c7, c10, 4
@@ -409,14 +413,15 @@ ENTRY(cpu_arm1020_switch_mm)
409413
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
410414
#endif /* CONFIG_MMU */
411415
ret lr
412-
416+
SYM_FUNC_END(cpu_arm1020_switch_mm)
417+
413418
/*
414419
* cpu_arm1020_set_pte(ptep, pte)
415420
*
416421
* Set a PTE and flush it out
417422
*/
418423
.align 5
419-
ENTRY(cpu_arm1020_set_pte_ext)
424+
SYM_TYPED_FUNC_START(cpu_arm1020_set_pte_ext)
420425
#ifdef CONFIG_MMU
421426
armv3_set_pte_ext
422427
mov r0, r0
@@ -427,6 +432,7 @@ ENTRY(cpu_arm1020_set_pte_ext)
427432
mcr p15, 0, r0, c7, c10, 4 @ drain WB
428433
#endif /* CONFIG_MMU */
429434
ret lr
435+
SYM_FUNC_END(cpu_arm1020_set_pte_ext)
430436

431437
.type __arm1020_setup, #function
432438
__arm1020_setup:

‎arch/arm/mm/proc-arm1020e.S‎

Lines changed: 15 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -57,18 +57,20 @@
5757
/*
5858
* cpu_arm1020e_proc_init()
5959
*/
60-
ENTRY(cpu_arm1020e_proc_init)
60+
SYM_TYPED_FUNC_START(cpu_arm1020e_proc_init)
6161
ret lr
62+
SYM_FUNC_END(cpu_arm1020e_proc_init)
6263

6364
/*
6465
* cpu_arm1020e_proc_fin()
6566
*/
66-
ENTRY(cpu_arm1020e_proc_fin)
67+
SYM_TYPED_FUNC_START(cpu_arm1020e_proc_fin)
6768
mrc p15, 0, r0, c1, c0, 0 @ ctrl register
6869
bic r0, r0, #0x1000 @ ...i............
6970
bic r0, r0, #0x000e @ ............wca.
7071
mcr p15, 0, r0, c1, c0, 0 @ disable caches
7172
ret lr
73+
SYM_FUNC_END(cpu_arm1020e_proc_fin)
7274

7375
/*
7476
* cpu_arm1020e_reset(loc)
@@ -81,7 +83,7 @@ ENTRY(cpu_arm1020e_proc_fin)
8183
*/
8284
.align 5
8385
.pushsection .idmap.text, "ax"
84-
ENTRY(cpu_arm1020e_reset)
86+
SYM_TYPED_FUNC_START(cpu_arm1020e_reset)
8587
mov ip, #0
8688
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
8789
mcr p15, 0, ip, c7, c10, 4 @ drain WB
@@ -93,16 +95,17 @@ ENTRY(cpu_arm1020e_reset)
9395
bic ip, ip, #0x1100 @ ...i...s........
9496
mcr p15, 0, ip, c1, c0, 0 @ ctrl register
9597
ret r0
96-
ENDPROC(cpu_arm1020e_reset)
98+
SYM_FUNC_END(cpu_arm1020e_reset)
9799
.popsection
98100

99101
/*
100102
* cpu_arm1020e_do_idle()
101103
*/
102104
.align 5
103-
ENTRY(cpu_arm1020e_do_idle)
105+
SYM_TYPED_FUNC_START(cpu_arm1020e_do_idle)
104106
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
105107
ret lr
108+
SYM_FUNC_END(cpu_arm1020e_do_idle)
106109

107110
/* ================================= CACHE ================================ */
108111

@@ -347,7 +350,7 @@ SYM_TYPED_FUNC_START(arm1020e_dma_unmap_area)
347350
SYM_FUNC_END(arm1020e_dma_unmap_area)
348351

349352
.align 5
350-
ENTRY(cpu_arm1020e_dcache_clean_area)
353+
SYM_TYPED_FUNC_START(cpu_arm1020e_dcache_clean_area)
351354
#ifndef CONFIG_CPU_DCACHE_DISABLE
352355
mov ip, #0
353356
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -356,6 +359,7 @@ ENTRY(cpu_arm1020e_dcache_clean_area)
356359
bhi 1b
357360
#endif
358361
ret lr
362+
SYM_FUNC_END(cpu_arm1020e_dcache_clean_area)
359363

360364
/* =============================== PageTable ============================== */
361365

@@ -367,7 +371,7 @@ ENTRY(cpu_arm1020e_dcache_clean_area)
367371
* pgd: new page tables
368372
*/
369373
.align 5
370-
ENTRY(cpu_arm1020e_switch_mm)
374+
SYM_TYPED_FUNC_START(cpu_arm1020e_switch_mm)
371375
#ifdef CONFIG_MMU
372376
#ifndef CONFIG_CPU_DCACHE_DISABLE
373377
mcr p15, 0, r3, c7, c10, 4
@@ -394,14 +398,15 @@ ENTRY(cpu_arm1020e_switch_mm)
394398
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
395399
#endif
396400
ret lr
397-
401+
SYM_FUNC_END(cpu_arm1020e_switch_mm)
402+
398403
/*
399404
* cpu_arm1020e_set_pte(ptep, pte)
400405
*
401406
* Set a PTE and flush it out
402407
*/
403408
.align 5
404-
ENTRY(cpu_arm1020e_set_pte_ext)
409+
SYM_TYPED_FUNC_START(cpu_arm1020e_set_pte_ext)
405410
#ifdef CONFIG_MMU
406411
armv3_set_pte_ext
407412
mov r0, r0
@@ -410,6 +415,7 @@ ENTRY(cpu_arm1020e_set_pte_ext)
410415
#endif
411416
#endif /* CONFIG_MMU */
412417
ret lr
418+
SYM_FUNC_END(cpu_arm1020e_set_pte_ext)
413419

414420
.type __arm1020e_setup, #function
415421
__arm1020e_setup:

‎arch/arm/mm/proc-arm1022.S‎

Lines changed: 15 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -57,18 +57,20 @@
5757
/*
5858
* cpu_arm1022_proc_init()
5959
*/
60-
ENTRY(cpu_arm1022_proc_init)
60+
SYM_TYPED_FUNC_START(cpu_arm1022_proc_init)
6161
ret lr
62+
SYM_FUNC_END(cpu_arm1022_proc_init)
6263

6364
/*
6465
* cpu_arm1022_proc_fin()
6566
*/
66-
ENTRY(cpu_arm1022_proc_fin)
67+
SYM_TYPED_FUNC_START(cpu_arm1022_proc_fin)
6768
mrc p15, 0, r0, c1, c0, 0 @ ctrl register
6869
bic r0, r0, #0x1000 @ ...i............
6970
bic r0, r0, #0x000e @ ............wca.
7071
mcr p15, 0, r0, c1, c0, 0 @ disable caches
7172
ret lr
73+
SYM_FUNC_END(cpu_arm1022_proc_fin)
7274

7375
/*
7476
* cpu_arm1022_reset(loc)
@@ -81,7 +83,7 @@ ENTRY(cpu_arm1022_proc_fin)
8183
*/
8284
.align 5
8385
.pushsection .idmap.text, "ax"
84-
ENTRY(cpu_arm1022_reset)
86+
SYM_TYPED_FUNC_START(cpu_arm1022_reset)
8587
mov ip, #0
8688
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
8789
mcr p15, 0, ip, c7, c10, 4 @ drain WB
@@ -93,16 +95,17 @@ ENTRY(cpu_arm1022_reset)
9395
bic ip, ip, #0x1100 @ ...i...s........
9496
mcr p15, 0, ip, c1, c0, 0 @ ctrl register
9597
ret r0
96-
ENDPROC(cpu_arm1022_reset)
98+
SYM_FUNC_END(cpu_arm1022_reset)
9799
.popsection
98100

99101
/*
100102
* cpu_arm1022_do_idle()
101103
*/
102104
.align 5
103-
ENTRY(cpu_arm1022_do_idle)
105+
SYM_TYPED_FUNC_START(cpu_arm1022_do_idle)
104106
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
105107
ret lr
108+
SYM_FUNC_END(cpu_arm1022_do_idle)
106109

107110
/* ================================= CACHE ================================ */
108111

@@ -346,7 +349,7 @@ SYM_TYPED_FUNC_START(arm1022_dma_unmap_area)
346349
SYM_FUNC_END(arm1022_dma_unmap_area)
347350

348351
.align 5
349-
ENTRY(cpu_arm1022_dcache_clean_area)
352+
SYM_TYPED_FUNC_START(cpu_arm1022_dcache_clean_area)
350353
#ifndef CONFIG_CPU_DCACHE_DISABLE
351354
mov ip, #0
352355
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
@@ -355,6 +358,7 @@ ENTRY(cpu_arm1022_dcache_clean_area)
355358
bhi 1b
356359
#endif
357360
ret lr
361+
SYM_FUNC_END(cpu_arm1022_dcache_clean_area)
358362

359363
/* =============================== PageTable ============================== */
360364

@@ -366,7 +370,7 @@ ENTRY(cpu_arm1022_dcache_clean_area)
366370
* pgd: new page tables
367371
*/
368372
.align 5
369-
ENTRY(cpu_arm1022_switch_mm)
373+
SYM_TYPED_FUNC_START(cpu_arm1022_switch_mm)
370374
#ifdef CONFIG_MMU
371375
#ifndef CONFIG_CPU_DCACHE_DISABLE
372376
mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
@@ -386,14 +390,15 @@ ENTRY(cpu_arm1022_switch_mm)
386390
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
387391
#endif
388392
ret lr
389-
393+
SYM_FUNC_END(cpu_arm1022_switch_mm)
394+
390395
/*
391396
* cpu_arm1022_set_pte_ext(ptep, pte, ext)
392397
*
393398
* Set a PTE and flush it out
394399
*/
395400
.align 5
396-
ENTRY(cpu_arm1022_set_pte_ext)
401+
SYM_TYPED_FUNC_START(cpu_arm1022_set_pte_ext)
397402
#ifdef CONFIG_MMU
398403
armv3_set_pte_ext
399404
mov r0, r0
@@ -402,6 +407,7 @@ ENTRY(cpu_arm1022_set_pte_ext)
402407
#endif
403408
#endif /* CONFIG_MMU */
404409
ret lr
410+
SYM_FUNC_END(cpu_arm1022_set_pte_ext)
405411

406412
.type __arm1022_setup, #function
407413
__arm1022_setup:

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