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TE-N-ShengjiuWangbroonie
TE-N-ShengjiuWang
authored and
broonie
committed
ASoC: fsl_spdif: Add new registers included on i.MX8ULP
There are some new registers added on i.MX8ULP, they are the SPDIF transmit Professional C channel registers, 192bit SPDIF receive C channel registers, and 192bit SPDIF transmit C channel registers. There are two output lines, SPDIF_OUT1 and SPDIF_OUT2, the original REG_SPDIF_STCSCH and REG_SPDIF_STCSCL are used for SPDIF_OUT1, the new REG_SPDIF_STCSPH and REG_SPDIF_STCSPL are used for SPDIF_OUT2, the 192bit SPDIF C channel registers are used for both. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1647408538-2982-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
1 parent b26f965 commit 638cec3

2 files changed

Lines changed: 65 additions & 1 deletion

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‎sound/soc/fsl/fsl_spdif.c‎

Lines changed: 51 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,7 @@ static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
5050
* @shared_root_clock: flag of sharing a clock source with others;
5151
* so the driver shouldn't set root clock rate
5252
* @raw_capture_mode: if raw capture mode support
53+
* @cchannel_192b: if there are registers for 192bits C channel data
5354
* @interrupts: interrupt number
5455
* @tx_burst: tx maxburst size
5556
* @rx_burst: rx maxburst size
@@ -59,6 +60,7 @@ struct fsl_spdif_soc_data {
5960
bool imx;
6061
bool shared_root_clock;
6162
bool raw_capture_mode;
63+
bool cchannel_192b;
6264
u32 interrupts;
6365
u32 tx_burst;
6466
u32 rx_burst;
@@ -196,6 +198,7 @@ static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = {
196198
.tx_burst = 2, /* Applied for EDMA */
197199
.rx_burst = 2, /* Applied for EDMA */
198200
.tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
201+
.cchannel_192b = true,
199202
};
200203

201204
/* Check if clk is a root clock that does not share clock source with others */
@@ -441,6 +444,23 @@ static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
441444
regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
442445

443446
dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
447+
448+
if (spdif_priv->soc->cchannel_192b) {
449+
ch_status = (bitrev8(ctrl->ch_status[0]) << 24) |
450+
(bitrev8(ctrl->ch_status[1]) << 16) |
451+
(bitrev8(ctrl->ch_status[2]) << 8) |
452+
bitrev8(ctrl->ch_status[3]);
453+
454+
regmap_update_bits(regmap, REG_SPDIF_SCR, 0x1000000, 0x1000000);
455+
456+
/*
457+
* The first 32bit should be in REG_SPDIF_STCCA_31_0 register,
458+
* but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP
459+
* then can get correct result with HDMI analyzer capture.
460+
* There is a hardware bug here.
461+
*/
462+
regmap_write(regmap, REG_SPDIF_STCCA_191_160, ch_status);
463+
}
444464
}
445465

446466
/* Set SPDIF PhaseConfig register for rx clock */
@@ -1229,6 +1249,8 @@ static const struct reg_default fsl_spdif_reg_defaults[] = {
12291249
{REG_SPDIF_STR, 0x00000000},
12301250
{REG_SPDIF_STCSCH, 0x00000000},
12311251
{REG_SPDIF_STCSCL, 0x00000000},
1252+
{REG_SPDIF_STCSPH, 0x00000000},
1253+
{REG_SPDIF_STCSPL, 0x00000000},
12321254
{REG_SPDIF_STC, 0x00020f00},
12331255
};
12341256

@@ -1248,8 +1270,22 @@ static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
12481270
case REG_SPDIF_SRQ:
12491271
case REG_SPDIF_STCSCH:
12501272
case REG_SPDIF_STCSCL:
1273+
case REG_SPDIF_STCSPH:
1274+
case REG_SPDIF_STCSPL:
12511275
case REG_SPDIF_SRFM:
12521276
case REG_SPDIF_STC:
1277+
case REG_SPDIF_SRCCA_31_0:
1278+
case REG_SPDIF_SRCCA_63_32:
1279+
case REG_SPDIF_SRCCA_95_64:
1280+
case REG_SPDIF_SRCCA_127_96:
1281+
case REG_SPDIF_SRCCA_159_128:
1282+
case REG_SPDIF_SRCCA_191_160:
1283+
case REG_SPDIF_STCCA_31_0:
1284+
case REG_SPDIF_STCCA_63_32:
1285+
case REG_SPDIF_STCCA_95_64:
1286+
case REG_SPDIF_STCCA_127_96:
1287+
case REG_SPDIF_STCCA_159_128:
1288+
case REG_SPDIF_STCCA_191_160:
12531289
return true;
12541290
default:
12551291
return false;
@@ -1268,6 +1304,12 @@ static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
12681304
case REG_SPDIF_SRU:
12691305
case REG_SPDIF_SRQ:
12701306
case REG_SPDIF_SRFM:
1307+
case REG_SPDIF_SRCCA_31_0:
1308+
case REG_SPDIF_SRCCA_63_32:
1309+
case REG_SPDIF_SRCCA_95_64:
1310+
case REG_SPDIF_SRCCA_127_96:
1311+
case REG_SPDIF_SRCCA_159_128:
1312+
case REG_SPDIF_SRCCA_191_160:
12711313
return true;
12721314
default:
12731315
return false;
@@ -1286,7 +1328,15 @@ static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
12861328
case REG_SPDIF_STR:
12871329
case REG_SPDIF_STCSCH:
12881330
case REG_SPDIF_STCSCL:
1331+
case REG_SPDIF_STCSPH:
1332+
case REG_SPDIF_STCSPL:
12891333
case REG_SPDIF_STC:
1334+
case REG_SPDIF_STCCA_31_0:
1335+
case REG_SPDIF_STCCA_63_32:
1336+
case REG_SPDIF_STCCA_95_64:
1337+
case REG_SPDIF_STCCA_127_96:
1338+
case REG_SPDIF_STCCA_159_128:
1339+
case REG_SPDIF_STCCA_191_160:
12901340
return true;
12911341
default:
12921342
return false;
@@ -1298,7 +1348,7 @@ static const struct regmap_config fsl_spdif_regmap_config = {
12981348
.reg_stride = 4,
12991349
.val_bits = 32,
13001350

1301-
.max_register = REG_SPDIF_STC,
1351+
.max_register = REG_SPDIF_STCCA_191_160,
13021352
.reg_defaults = fsl_spdif_reg_defaults,
13031353
.num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
13041354
.readable_reg = fsl_spdif_readable_reg,

‎sound/soc/fsl/fsl_spdif.h‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,23 @@
3131
#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
3232
#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
3333
#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
34+
#define REG_SPDIF_STCSPH 0x3C /* SPDIFTxCChannel_Prof_h Register */
35+
#define REG_SPDIF_STCSPL 0x40 /* SPDIFTxCChannel_Prof_l Register */
3436
#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
3537
#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
3638

39+
#define REG_SPDIF_SRCCA_31_0 0x60 /* SPDIF receive C channel register, bits 31-0 */
40+
#define REG_SPDIF_SRCCA_63_32 0x64 /* SPDIF receive C channel register, bits 63-32 */
41+
#define REG_SPDIF_SRCCA_95_64 0x68 /* SPDIF receive C channel register, bits 95-64 */
42+
#define REG_SPDIF_SRCCA_127_96 0x6C /* SPDIF receive C channel register, bits 127-96 */
43+
#define REG_SPDIF_SRCCA_159_128 0x70 /* SPDIF receive C channel register, bits 159-128 */
44+
#define REG_SPDIF_SRCCA_191_160 0x74 /* SPDIF receive C channel register, bits 191-160 */
45+
#define REG_SPDIF_STCCA_31_0 0x78 /* SPDIF transmit C channel register, bits 31-0 */
46+
#define REG_SPDIF_STCCA_63_32 0x7C /* SPDIF transmit C channel register, bits 63-32 */
47+
#define REG_SPDIF_STCCA_95_64 0x80 /* SPDIF transmit C channel register, bits 95-64 */
48+
#define REG_SPDIF_STCCA_127_96 0x84 /* SPDIF transmit C channel register, bits 127-96 */
49+
#define REG_SPDIF_STCCA_159_128 0x88 /* SPDIF transmit C channel register, bits 159-128 */
50+
#define REG_SPDIF_STCCA_191_160 0x8C /* SPDIF transmit C channel register, bits 191-160 */
3751

3852
/* SPDIF Configuration register */
3953
#define SCR_RXFIFO_CTL_OFFSET 23

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