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Dinh Nguyenbebarino
Dinh Nguyen
authored and
bebarino
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clk: agilex/stratix10: fix bypass representation
Each of these clocks(s2f_usr0/1, sdmmc_clk, gpio_db, emac_ptp, emac0/1/2) have a bypass setting that can use the boot_clk. The previous representation was not correct. Fix the representation. Fixes: 80c6b7a ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210611025201.118799-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
1 parent efbe21d commit 6855ee8

2 files changed

Lines changed: 91 additions & 21 deletions

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‎drivers/clk/socfpga/clk-agilex.c‎

Lines changed: 46 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -186,6 +186,41 @@ static const struct clk_parent_data noc_mux[] = {
186186
.name = "boot_clk", },
187187
};
188188

189+
static const struct clk_parent_data sdmmc_mux[] = {
190+
{ .fw_name = "sdmmc_free_clk",
191+
.name = "sdmmc_free_clk", },
192+
{ .fw_name = "boot_clk",
193+
.name = "boot_clk", },
194+
};
195+
196+
static const struct clk_parent_data s2f_user1_mux[] = {
197+
{ .fw_name = "s2f_user1_free_clk",
198+
.name = "s2f_user1_free_clk", },
199+
{ .fw_name = "boot_clk",
200+
.name = "boot_clk", },
201+
};
202+
203+
static const struct clk_parent_data psi_mux[] = {
204+
{ .fw_name = "psi_ref_free_clk",
205+
.name = "psi_ref_free_clk", },
206+
{ .fw_name = "boot_clk",
207+
.name = "boot_clk", },
208+
};
209+
210+
static const struct clk_parent_data gpio_db_mux[] = {
211+
{ .fw_name = "gpio_db_free_clk",
212+
.name = "gpio_db_free_clk", },
213+
{ .fw_name = "boot_clk",
214+
.name = "boot_clk", },
215+
};
216+
217+
static const struct clk_parent_data emac_ptp_mux[] = {
218+
{ .fw_name = "emac_ptp_free_clk",
219+
.name = "emac_ptp_free_clk", },
220+
{ .fw_name = "boot_clk",
221+
.name = "boot_clk", },
222+
};
223+
189224
/* clocks in AO (always on) controller */
190225
static const struct stratix10_pll_clock agilex_pll_clks[] = {
191226
{ AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
@@ -234,7 +269,7 @@ static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
234269
{ AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
235270
ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3},
236271
{ AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
237-
ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0x88, 4},
272+
ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0, 0},
238273
{ AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
239274
ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0},
240275
{ AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
@@ -276,16 +311,16 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
276311
1, 0, 0, 0, 0x94, 27, 0},
277312
{ AGILEX_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
278313
2, 0, 0, 0, 0x94, 28, 0},
279-
{ AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0x7C,
280-
3, 0, 0, 0, 0, 0, 0},
281-
{ AGILEX_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0x7C,
282-
4, 0x98, 0, 16, 0, 0, 0},
283-
{ AGILEX_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0x7C,
284-
5, 0, 0, 0, 0, 0, 4},
285-
{ AGILEX_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0x7C,
286-
6, 0, 0, 0, 0, 0, 0},
287-
{ AGILEX_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0x7C,
288-
7, 0, 0, 0, 0, 0, 0},
314+
{ AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, ARRAY_SIZE(emac_ptp_mux), 0, 0x7C,
315+
3, 0, 0, 0, 0x88, 2, 0},
316+
{ AGILEX_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, ARRAY_SIZE(gpio_db_mux), 0, 0x7C,
317+
4, 0x98, 0, 16, 0x88, 3, 0},
318+
{ AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C,
319+
5, 0, 0, 0, 0x88, 4, 4},
320+
{ AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C,
321+
6, 0, 0, 0, 0x88, 5, 0},
322+
{ AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C,
323+
7, 0, 0, 0, 0x88, 6, 0},
289324
{ AGILEX_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
290325
8, 0, 0, 0, 0, 0, 0},
291326
{ AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,

‎drivers/clk/socfpga/clk-s10.c‎

Lines changed: 45 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,41 @@ static const struct clk_parent_data mpu_free_mux[] = {
144144
.name = "f2s-free-clk", },
145145
};
146146

147+
static const struct clk_parent_data sdmmc_mux[] = {
148+
{ .fw_name = "sdmmc_free_clk",
149+
.name = "sdmmc_free_clk", },
150+
{ .fw_name = "boot_clk",
151+
.name = "boot_clk", },
152+
};
153+
154+
static const struct clk_parent_data s2f_user1_mux[] = {
155+
{ .fw_name = "s2f_user1_free_clk",
156+
.name = "s2f_user1_free_clk", },
157+
{ .fw_name = "boot_clk",
158+
.name = "boot_clk", },
159+
};
160+
161+
static const struct clk_parent_data psi_mux[] = {
162+
{ .fw_name = "psi_ref_free_clk",
163+
.name = "psi_ref_free_clk", },
164+
{ .fw_name = "boot_clk",
165+
.name = "boot_clk", },
166+
};
167+
168+
static const struct clk_parent_data gpio_db_mux[] = {
169+
{ .fw_name = "gpio_db_free_clk",
170+
.name = "gpio_db_free_clk", },
171+
{ .fw_name = "boot_clk",
172+
.name = "boot_clk", },
173+
};
174+
175+
static const struct clk_parent_data emac_ptp_mux[] = {
176+
{ .fw_name = "emac_ptp_free_clk",
177+
.name = "emac_ptp_free_clk", },
178+
{ .fw_name = "boot_clk",
179+
.name = "boot_clk", },
180+
};
181+
147182
/* clocks in AO (always on) controller */
148183
static const struct stratix10_pll_clock s10_pll_clks[] = {
149184
{ STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
@@ -247,16 +282,16 @@ static const struct stratix10_gate_clock s10_gate_clks[] = {
247282
1, 0, 0, 0, 0xDC, 27, 0},
248283
{ STRATIX10_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
249284
2, 0, 0, 0, 0xDC, 28, 0},
250-
{ STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0xA4,
251-
3, 0, 0, 0, 0, 0, 0},
252-
{ STRATIX10_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0xA4,
253-
4, 0xE0, 0, 16, 0, 0, 0},
254-
{ STRATIX10_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0xA4,
255-
5, 0, 0, 0, 0, 0, 4},
256-
{ STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0xA4,
257-
6, 0, 0, 0, 0, 0, 0},
258-
{ STRATIX10_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0xA4,
259-
7, 0, 0, 0, 0, 0, 0},
285+
{ STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, ARRAY_SIZE(emac_ptp_mux), 0, 0xA4,
286+
3, 0, 0, 0, 0xB0, 2, 0},
287+
{ STRATIX10_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, ARRAY_SIZE(gpio_db_mux), 0, 0xA4,
288+
4, 0xE0, 0, 16, 0xB0, 3, 0},
289+
{ STRATIX10_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0xA4,
290+
5, 0, 0, 0, 0xB0, 4, 4},
291+
{ STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0xA4,
292+
6, 0, 0, 0, 0xB0, 5, 0},
293+
{ STRATIX10_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0xA4,
294+
7, 0, 0, 0, 0xB0, 6, 0},
260295
{ STRATIX10_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
261296
8, 0, 0, 0, 0, 0, 0},
262297
{ STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,

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