|
224 | 224 | clock-frequency = <50000000>; |
225 | 225 | }; |
226 | 226 |
|
227 | | - i2cslimpro { |
| 227 | + i2c { |
228 | 228 | compatible = "apm,xgene-slimpro-i2c"; |
229 | 229 | mboxes = <&mailbox 0>; |
230 | 230 | }; |
|
295 | 295 |
|
296 | 296 | socplldiv2: socplldiv2 { |
297 | 297 | compatible = "fixed-factor-clock"; |
298 | | - #clock-cells = <1>; |
| 298 | + #clock-cells = <0>; |
299 | 299 | clocks = <&socpll 0>; |
300 | 300 | clock-mult = <1>; |
301 | 301 | clock-div = <2>; |
|
305 | 305 | ahbclk: ahbclk@17000000 { |
306 | 306 | compatible = "apm,xgene-device-clock"; |
307 | 307 | #clock-cells = <1>; |
308 | | - clocks = <&socplldiv2 0>; |
| 308 | + clocks = <&socplldiv2>; |
309 | 309 | reg = <0x0 0x17000000 0x0 0x2000>; |
310 | 310 | reg-names = "div-reg"; |
311 | 311 | divider-offset = <0x164>; |
|
329 | 329 | sdioclk: sdioclk@1f2ac000 { |
330 | 330 | compatible = "apm,xgene-device-clock"; |
331 | 331 | #clock-cells = <1>; |
332 | | - clocks = <&socplldiv2 0>; |
| 332 | + clocks = <&socplldiv2>; |
333 | 333 | reg = <0x0 0x1f2ac000 0x0 0x1000 |
334 | 334 | 0x0 0x17000000 0x0 0x2000>; |
335 | 335 | reg-names = "csr-reg", "div-reg"; |
|
346 | 346 | pcie0clk: pcie0clk@1f2bc000 { |
347 | 347 | compatible = "apm,xgene-device-clock"; |
348 | 348 | #clock-cells = <1>; |
349 | | - clocks = <&socplldiv2 0>; |
| 349 | + clocks = <&socplldiv2>; |
350 | 350 | reg = <0x0 0x1f2bc000 0x0 0x1000>; |
351 | 351 | reg-names = "csr-reg"; |
352 | 352 | clock-output-names = "pcie0clk"; |
|
355 | 355 | pcie1clk: pcie1clk@1f2cc000 { |
356 | 356 | compatible = "apm,xgene-device-clock"; |
357 | 357 | #clock-cells = <1>; |
358 | | - clocks = <&socplldiv2 0>; |
| 358 | + clocks = <&socplldiv2>; |
359 | 359 | reg = <0x0 0x1f2cc000 0x0 0x1000>; |
360 | 360 | reg-names = "csr-reg"; |
361 | 361 | clock-output-names = "pcie1clk"; |
|
364 | 364 | xge0clk: xge0clk@1f61c000 { |
365 | 365 | compatible = "apm,xgene-device-clock"; |
366 | 366 | #clock-cells = <1>; |
367 | | - clocks = <&socplldiv2 0>; |
| 367 | + clocks = <&socplldiv2>; |
368 | 368 | reg = <0x0 0x1f61c000 0x0 0x1000>; |
369 | 369 | reg-names = "csr-reg"; |
370 | 370 | enable-mask = <0x3>; |
|
375 | 375 | xge1clk: xge1clk@1f62c000 { |
376 | 376 | compatible = "apm,xgene-device-clock"; |
377 | 377 | #clock-cells = <1>; |
378 | | - clocks = <&socplldiv2 0>; |
| 378 | + clocks = <&socplldiv2>; |
379 | 379 | reg = <0x0 0x1f62c000 0x0 0x1000>; |
380 | 380 | reg-names = "csr-reg"; |
381 | 381 | enable-mask = <0x3>; |
|
386 | 386 | rngpkaclk: rngpkaclk@17000000 { |
387 | 387 | compatible = "apm,xgene-device-clock"; |
388 | 388 | #clock-cells = <1>; |
389 | | - clocks = <&socplldiv2 0>; |
| 389 | + clocks = <&socplldiv2>; |
390 | 390 | reg = <0x0 0x17000000 0x0 0x2000>; |
391 | 391 | reg-names = "csr-reg"; |
392 | 392 | csr-offset = <0xc>; |
|
417 | 417 |
|
418 | 418 | reboot: reboot@17000014 { |
419 | 419 | compatible = "syscon-reboot"; |
| 420 | + reg = <0x0 0x17000014 0x0 0x4>; |
420 | 421 | regmap = <&scu>; |
421 | 422 | offset = <0x14>; |
422 | 423 | mask = <0x1>; |
|
799 | 800 | compatible = "snps,designware-i2c"; |
800 | 801 | reg = <0x0 0x10511000 0x0 0x1000>; |
801 | 802 | interrupts = <0 0x45 0x4>; |
802 | | - #clock-cells = <1>; |
803 | 803 | clocks = <&sbapbclk 0>; |
804 | 804 | }; |
805 | 805 |
|
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