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Merge branch 'for-next/sysregs' into for-next/core
* for-next/sysregs: (39 commits) arm64/sysreg: Remove duplicate definitions from asm/sysreg.h arm64/sysreg: Convert ID_DFR1_EL1 to automatic generation arm64/sysreg: Convert ID_DFR0_EL1 to automatic generation arm64/sysreg: Convert ID_AFR0_EL1 to automatic generation arm64/sysreg: Convert ID_MMFR5_EL1 to automatic generation arm64/sysreg: Convert MVFR2_EL1 to automatic generation arm64/sysreg: Convert MVFR1_EL1 to automatic generation arm64/sysreg: Convert MVFR0_EL1 to automatic generation arm64/sysreg: Convert ID_PFR2_EL1 to automatic generation arm64/sysreg: Convert ID_PFR1_EL1 to automatic generation arm64/sysreg: Convert ID_PFR0_EL1 to automatic generation arm64/sysreg: Convert ID_ISAR6_EL1 to automatic generation arm64/sysreg: Convert ID_ISAR5_EL1 to automatic generation arm64/sysreg: Convert ID_ISAR4_EL1 to automatic generation arm64/sysreg: Convert ID_ISAR3_EL1 to automatic generation arm64/sysreg: Convert ID_ISAR2_EL1 to automatic generation arm64/sysreg: Convert ID_ISAR1_EL1 to automatic generation arm64/sysreg: Convert ID_ISAR0_EL1 to automatic generation arm64/sysreg: Convert ID_MMFR4_EL1 to automatic generation arm64/sysreg: Convert ID_MMFR3_EL1 to automatic generation ...
2 parents 75bc81d + acb3f4b commit 70b1c62

6 files changed

Lines changed: 862 additions & 246 deletions

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‎arch/arm64/include/asm/sysreg.h‎

Lines changed: 0 additions & 138 deletions
Original file line numberDiff line numberDiff line change
@@ -169,31 +169,6 @@
169169
#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
170170
#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
171171

172-
#define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
173-
#define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
174-
#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4)
175-
#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
176-
#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
177-
#define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
178-
#define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
179-
#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
180-
#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
181-
#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
182-
#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
183-
#define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6)
184-
185-
#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
186-
#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
187-
#define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
188-
#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
189-
#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
190-
#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
191-
#define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7)
192-
193-
#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
194-
#define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
195-
#define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
196-
197172
#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
198173
#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
199174
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
@@ -696,112 +671,6 @@
696671
#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48
697672
#endif
698673

699-
#define ID_DFR0_PERFMON_SHIFT 24
700-
701-
#define ID_DFR0_PERFMON_8_0 0x3
702-
#define ID_DFR0_PERFMON_8_1 0x4
703-
#define ID_DFR0_PERFMON_8_4 0x5
704-
#define ID_DFR0_PERFMON_8_5 0x6
705-
706-
#define ID_ISAR4_SWP_FRAC_SHIFT 28
707-
#define ID_ISAR4_PSR_M_SHIFT 24
708-
#define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT 20
709-
#define ID_ISAR4_BARRIER_SHIFT 16
710-
#define ID_ISAR4_SMC_SHIFT 12
711-
#define ID_ISAR4_WRITEBACK_SHIFT 8
712-
#define ID_ISAR4_WITHSHIFTS_SHIFT 4
713-
#define ID_ISAR4_UNPRIV_SHIFT 0
714-
715-
#define ID_DFR1_MTPMU_SHIFT 0
716-
717-
#define ID_ISAR0_DIVIDE_SHIFT 24
718-
#define ID_ISAR0_DEBUG_SHIFT 20
719-
#define ID_ISAR0_COPROC_SHIFT 16
720-
#define ID_ISAR0_CMPBRANCH_SHIFT 12
721-
#define ID_ISAR0_BITFIELD_SHIFT 8
722-
#define ID_ISAR0_BITCOUNT_SHIFT 4
723-
#define ID_ISAR0_SWAP_SHIFT 0
724-
725-
#define ID_ISAR5_RDM_SHIFT 24
726-
#define ID_ISAR5_CRC32_SHIFT 16
727-
#define ID_ISAR5_SHA2_SHIFT 12
728-
#define ID_ISAR5_SHA1_SHIFT 8
729-
#define ID_ISAR5_AES_SHIFT 4
730-
#define ID_ISAR5_SEVL_SHIFT 0
731-
732-
#define ID_ISAR6_I8MM_SHIFT 24
733-
#define ID_ISAR6_BF16_SHIFT 20
734-
#define ID_ISAR6_SPECRES_SHIFT 16
735-
#define ID_ISAR6_SB_SHIFT 12
736-
#define ID_ISAR6_FHM_SHIFT 8
737-
#define ID_ISAR6_DP_SHIFT 4
738-
#define ID_ISAR6_JSCVT_SHIFT 0
739-
740-
#define ID_MMFR0_INNERSHR_SHIFT 28
741-
#define ID_MMFR0_FCSE_SHIFT 24
742-
#define ID_MMFR0_AUXREG_SHIFT 20
743-
#define ID_MMFR0_TCM_SHIFT 16
744-
#define ID_MMFR0_SHARELVL_SHIFT 12
745-
#define ID_MMFR0_OUTERSHR_SHIFT 8
746-
#define ID_MMFR0_PMSA_SHIFT 4
747-
#define ID_MMFR0_VMSA_SHIFT 0
748-
749-
#define ID_MMFR4_EVT_SHIFT 28
750-
#define ID_MMFR4_CCIDX_SHIFT 24
751-
#define ID_MMFR4_LSM_SHIFT 20
752-
#define ID_MMFR4_HPDS_SHIFT 16
753-
#define ID_MMFR4_CNP_SHIFT 12
754-
#define ID_MMFR4_XNX_SHIFT 8
755-
#define ID_MMFR4_AC2_SHIFT 4
756-
#define ID_MMFR4_SPECSEI_SHIFT 0
757-
758-
#define ID_MMFR5_ETS_SHIFT 0
759-
760-
#define ID_PFR0_DIT_SHIFT 24
761-
#define ID_PFR0_CSV2_SHIFT 16
762-
#define ID_PFR0_STATE3_SHIFT 12
763-
#define ID_PFR0_STATE2_SHIFT 8
764-
#define ID_PFR0_STATE1_SHIFT 4
765-
#define ID_PFR0_STATE0_SHIFT 0
766-
767-
#define ID_DFR0_PERFMON_SHIFT 24
768-
#define ID_DFR0_MPROFDBG_SHIFT 20
769-
#define ID_DFR0_MMAPTRC_SHIFT 16
770-
#define ID_DFR0_COPTRC_SHIFT 12
771-
#define ID_DFR0_MMAPDBG_SHIFT 8
772-
#define ID_DFR0_COPSDBG_SHIFT 4
773-
#define ID_DFR0_COPDBG_SHIFT 0
774-
775-
#define ID_PFR2_SSBS_SHIFT 4
776-
#define ID_PFR2_CSV3_SHIFT 0
777-
778-
#define MVFR0_FPROUND_SHIFT 28
779-
#define MVFR0_FPSHVEC_SHIFT 24
780-
#define MVFR0_FPSQRT_SHIFT 20
781-
#define MVFR0_FPDIVIDE_SHIFT 16
782-
#define MVFR0_FPTRAP_SHIFT 12
783-
#define MVFR0_FPDP_SHIFT 8
784-
#define MVFR0_FPSP_SHIFT 4
785-
#define MVFR0_SIMD_SHIFT 0
786-
787-
#define MVFR1_SIMDFMAC_SHIFT 28
788-
#define MVFR1_FPHP_SHIFT 24
789-
#define MVFR1_SIMDHP_SHIFT 20
790-
#define MVFR1_SIMDSP_SHIFT 16
791-
#define MVFR1_SIMDINT_SHIFT 12
792-
#define MVFR1_SIMDLS_SHIFT 8
793-
#define MVFR1_FPDNAN_SHIFT 4
794-
#define MVFR1_FPFTZ_SHIFT 0
795-
796-
#define ID_PFR1_GIC_SHIFT 28
797-
#define ID_PFR1_VIRT_FRAC_SHIFT 24
798-
#define ID_PFR1_SEC_FRAC_SHIFT 20
799-
#define ID_PFR1_GENTIMER_SHIFT 16
800-
#define ID_PFR1_VIRTUALIZATION_SHIFT 12
801-
#define ID_PFR1_MPROGMOD_SHIFT 8
802-
#define ID_PFR1_SECURITY_SHIFT 4
803-
#define ID_PFR1_PROGMOD_SHIFT 0
804-
805674
#if defined(CONFIG_ARM64_4K_PAGES)
806675
#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
807676
#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
@@ -819,9 +688,6 @@
819688
#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
820689
#endif
821690

822-
#define MVFR2_FPMISC_SHIFT 4
823-
#define MVFR2_SIMDMISC_SHIFT 0
824-
825691
#define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
826692
#define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
827693

@@ -855,10 +721,6 @@
855721
#define SYS_RGSR_EL1_SEED_SHIFT 8
856722
#define SYS_RGSR_EL1_SEED_MASK 0xffffUL
857723

858-
/* GMID_EL1 field definitions */
859-
#define GMID_EL1_BS_SHIFT 0
860-
#define GMID_EL1_BS_SIZE 4
861-
862724
/* TFSR{,E0}_EL1 bit definitions */
863725
#define SYS_TFSR_EL1_TF0_SHIFT 0
864726
#define SYS_TFSR_EL1_TF1_SHIFT 1

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