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Merge branch 'clk-qcom' into clk-next
* clk-qcom: Revert "clk: qcom: regmap-mux: add pipe clk implementation" Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks" Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks" clk: qcom: rcg2: Cache CFG register updates for parked RCGs clk: qcom: add sc8280xp GCC driver dt-bindings: clock: Add Qualcomm SC8280XP GCC bindings clk: qcom: gcc-msm8976: Add modem reset dt-bindings: clk: qcom: gcc-msm8976: Add modem reset clk: qcom: gcc-msm8976: Set floor ops for SDCC dt-bindings: clock: qcom,gcc-apq8064: Fix typo in compatible and split apq8084 clk: qcom: smd: Update MSM8976 RPM clocks. clk: qcom: gcc-msm8998: add SSC-related clocks dt-bindings: clock: gcc-msm8998: Add definitions of SSC-related clocks dt-bindings: clock: qcom,rpmcc: add clocks property dt-bindings: clock: qcom,rpmcc: convert to dtschema clk: qcom: lpass: Add support for LPASS clock controller for SC7280 dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks clk: qcom: regmap-mux: add pipe clk implementation
2 parents d75c26a + c17f8fd commit 71cc785

22 files changed

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‎Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml‎

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See also:
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- dt-bindings/clock/qcom,gcc-msm8960.h
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- dt-bindings/reset/qcom,gcc-msm8960.h
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- dt-bindings/clock/qcom,gcc-apq8084.h
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- dt-bindings/reset/qcom,gcc-apq8084.h
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properties:
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compatible:
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const: qcom,gcc-apq8084
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const: qcom,gcc-apq8064
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nvmem-cells:
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minItems: 1

‎Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for APQ8084
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on APQ8084.
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See also::
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- dt-bindings/clock/qcom,gcc-apq8084.h
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- dt-bindings/reset/qcom,gcc-apq8084.h
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allOf:
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- $ref: qcom,gcc.yaml#
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properties:
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compatible:
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const: qcom,gcc-apq8084
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required:
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- compatible
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unevaluatedProperties: false
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examples:
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- |
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clock-controller@fc400000 {
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compatible = "qcom,gcc-apq8084";
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reg = <0xfc400000 0x4000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on SC8280xp.
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See also:
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- include/dt-bindings/clock/qcom,gcc-sc8280xp.h
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properties:
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compatible:
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const: qcom,gcc-sc8280xp
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clocks:
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items:
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- description: XO reference clock
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- description: Sleep clock
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- description: UFS memory first RX symbol clock
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- description: UFS memory second RX symbol clock
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- description: UFS memory first TX symbol clock
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- description: UFS card first RX symbol clock
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- description: UFS card second RX symbol clock
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- description: UFS card first TX symbol clock
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- description: Primary USB SuperSpeed pipe clock
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- description: USB4 PHY pipegmux clock source
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- description: USB4 PHY DP gmux clock source
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- description: USB4 PHY sys piegmux clock source
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- description: USB4 PHY PCIe pipe clock
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- description: USB4 PHY router max pipe clock
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- description: Primary USB4 RX0 clock
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- description: Primary USB4 RX1 clock
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- description: Secondary USB SuperSpeed pipe clock
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- description: Second USB4 PHY pipegmux clock source
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- description: Second USB4 PHY DP gmux clock source
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- description: Second USB4 PHY sys pipegmux clock source
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- description: Second USB4 PHY PCIe pipe clock
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- description: Second USB4 PHY router max pipe clock
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- description: Secondary USB4 RX0 clock
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- description: Secondary USB4 RX1 clock
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- description: Multiport USB first SupserSpeed pipe clock
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- description: Multiport USB second SuperSpeed pipe clock
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- description: PCIe 2a pipe clock
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- description: PCIe 2b pipe clock
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- description: PCIe 3a pipe clock
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- description: PCIe 3b pipe clock
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- description: PCIe 4 pipe clock
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- description: First EMAC controller reference clock
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- description: Second EMAC controller reference clock
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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protected-clocks:
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maxItems: 389
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required:
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- compatible
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- clocks
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- reg
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,gcc-sc8280xp";
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reg = <0x00100000 0x1f0000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&ufs_phy_rx_symbol_0_clk>,
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<&ufs_phy_rx_symbol_1_clk>,
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<&ufs_phy_tx_symbol_0_clk>,
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<&ufs_card_rx_symbol_0_clk>,
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<&ufs_card_rx_symbol_1_clk>,
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<&ufs_card_tx_symbol_0_clk>,
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<&usb_0_ssphy>,
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<&gcc_usb4_phy_pipegmux_clk_src>,
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<&gcc_usb4_phy_dp_gmux_clk_src>,
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<&gcc_usb4_phy_sys_pipegmux_clk_src>,
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<&usb4_phy_gcc_usb4_pcie_pipe_clk>,
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<&usb4_phy_gcc_usb4rtr_max_pipe_clk>,
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<&qusb4phy_gcc_usb4_rx0_clk>,
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<&qusb4phy_gcc_usb4_rx1_clk>,
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<&usb_1_ssphy>,
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<&gcc_usb4_1_phy_pipegmux_clk_src>,
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<&gcc_usb4_1_phy_dp_gmux_clk_src>,
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<&gcc_usb4_1_phy_sys_pipegmux_clk_src>,
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<&usb4_1_phy_gcc_usb4_pcie_pipe_clk>,
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<&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>,
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<&qusb4phy_1_gcc_usb4_rx0_clk>,
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<&qusb4phy_1_gcc_usb4_rx1_clk>,
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<&usb_2_ssphy>,
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<&usb_3_ssphy>,
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<&pcie2a_lane>,
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<&pcie2b_lane>,
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<&pcie3a_lane>,
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<&pcie3b_lane>,
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<&pcie4_lane>,
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<&rxc0_ref_clk>,
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<&rxc1_ref_clk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,rpmcc.txt‎

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‎Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,rpmcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm RPM Clock Controller
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description: |
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The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> and
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come in pairs:: FOO_CLK followed by FOO_A_CLK. The latter clock is
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an "active" clock, which means that the consumer only care that the clock is
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available when the apps CPU subsystem is active, i.e. not suspended or in
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deep idle. If it is important that the clock keeps running during system
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suspend, you need to specify the non-active clock, the one not containing
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*_A_* in the enumerator name.
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properties:
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compatible:
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items:
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- enum:
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- qcom,rpmcc-apq8060
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- qcom,rpmcc-apq8064
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- qcom,rpmcc-ipq806x
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- qcom,rpmcc-mdm9607
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- qcom,rpmcc-msm8226
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- qcom,rpmcc-msm8660
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- qcom,rpmcc-msm8916
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- qcom,rpmcc-msm8936
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- qcom,rpmcc-msm8953
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- qcom,rpmcc-msm8974
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- qcom,rpmcc-msm8976
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- qcom,rpmcc-msm8992
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- qcom,rpmcc-msm8994
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- qcom,rpmcc-msm8996
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- qcom,rpmcc-msm8998
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- qcom,rpmcc-qcm2290
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- qcom,rpmcc-qcs404
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- qcom,rpmcc-sdm660
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- qcom,rpmcc-sm6115
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- qcom,rpmcc-sm6125
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- const: qcom,rpmcc
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'#clock-cells':
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const: 1
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clocks:
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maxItems: 1
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clock-names:
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const: xo
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required:
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- compatible
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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rpm {
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rpm-requests {
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compatible = "qcom,rpm-msm8916";
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qcom,smd-channels = "rpm_requests";
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clock-controller {
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compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
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#clock-cells = <1>;
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};
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};
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};

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