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244 | 244 | #size-cells = <0>; |
245 | 245 |
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246 | 246 | /* These power domains are grouped by VD_LOGIC */ |
247 | | - pd_usb@PX30_PD_USB { |
| 247 | + power-domain@PX30_PD_USB { |
248 | 248 | reg = <PX30_PD_USB>; |
249 | 249 | clocks = <&cru HCLK_HOST>, |
250 | 250 | <&cru HCLK_OTG>, |
251 | 251 | <&cru SCLK_OTG_ADP>; |
252 | 252 | pm_qos = <&qos_usb_host>, <&qos_usb_otg>; |
| 253 | + #power-domain-cells = <0>; |
253 | 254 | }; |
254 | | - pd_sdcard@PX30_PD_SDCARD { |
| 255 | + power-domain@PX30_PD_SDCARD { |
255 | 256 | reg = <PX30_PD_SDCARD>; |
256 | 257 | clocks = <&cru HCLK_SDMMC>, |
257 | 258 | <&cru SCLK_SDMMC>; |
258 | 259 | pm_qos = <&qos_sdmmc>; |
| 260 | + #power-domain-cells = <0>; |
259 | 261 | }; |
260 | | - pd_gmac@PX30_PD_GMAC { |
| 262 | + power-domain@PX30_PD_GMAC { |
261 | 263 | reg = <PX30_PD_GMAC>; |
262 | 264 | clocks = <&cru ACLK_GMAC>, |
263 | 265 | <&cru PCLK_GMAC>, |
264 | 266 | <&cru SCLK_MAC_REF>, |
265 | 267 | <&cru SCLK_GMAC_RX_TX>; |
266 | 268 | pm_qos = <&qos_gmac>; |
| 269 | + #power-domain-cells = <0>; |
267 | 270 | }; |
268 | | - pd_mmc_nand@PX30_PD_MMC_NAND { |
| 271 | + power-domain@PX30_PD_MMC_NAND { |
269 | 272 | reg = <PX30_PD_MMC_NAND>; |
270 | 273 | clocks = <&cru HCLK_NANDC>, |
271 | 274 | <&cru HCLK_EMMC>, |
|
277 | 280 | <&cru SCLK_SFC>; |
278 | 281 | pm_qos = <&qos_emmc>, <&qos_nand>, |
279 | 282 | <&qos_sdio>, <&qos_sfc>; |
| 283 | + #power-domain-cells = <0>; |
280 | 284 | }; |
281 | | - pd_vpu@PX30_PD_VPU { |
| 285 | + power-domain@PX30_PD_VPU { |
282 | 286 | reg = <PX30_PD_VPU>; |
283 | 287 | clocks = <&cru ACLK_VPU>, |
284 | 288 | <&cru HCLK_VPU>, |
285 | 289 | <&cru SCLK_CORE_VPU>; |
286 | 290 | pm_qos = <&qos_vpu>, <&qos_vpu_r128>; |
| 291 | + #power-domain-cells = <0>; |
287 | 292 | }; |
288 | | - pd_vo@PX30_PD_VO { |
| 293 | + power-domain@PX30_PD_VO { |
289 | 294 | reg = <PX30_PD_VO>; |
290 | 295 | clocks = <&cru ACLK_RGA>, |
291 | 296 | <&cru ACLK_VOPB>, |
|
300 | 305 | <&cru SCLK_VOPB_PWM>; |
301 | 306 | pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, |
302 | 307 | <&qos_vop_m0>, <&qos_vop_m1>; |
| 308 | + #power-domain-cells = <0>; |
303 | 309 | }; |
304 | | - pd_vi@PX30_PD_VI { |
| 310 | + power-domain@PX30_PD_VI { |
305 | 311 | reg = <PX30_PD_VI>; |
306 | 312 | clocks = <&cru ACLK_CIF>, |
307 | 313 | <&cru ACLK_ISP>, |
|
311 | 317 | pm_qos = <&qos_isp_128>, <&qos_isp_rd>, |
312 | 318 | <&qos_isp_wr>, <&qos_isp_m1>, |
313 | 319 | <&qos_vip>; |
| 320 | + #power-domain-cells = <0>; |
314 | 321 | }; |
315 | | - pd_gpu@PX30_PD_GPU { |
| 322 | + power-domain@PX30_PD_GPU { |
316 | 323 | reg = <PX30_PD_GPU>; |
317 | 324 | clocks = <&cru SCLK_GPU>; |
318 | 325 | pm_qos = <&qos_gpu>; |
| 326 | + #power-domain-cells = <0>; |
319 | 327 | }; |
320 | 328 | }; |
321 | 329 | }; |
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814 | 822 | #address-cells = <1>; |
815 | 823 | #size-cells = <1>; |
816 | 824 |
|
817 | | - u2phy: usb2-phy@100 { |
| 825 | + u2phy: usb2phy@100 { |
818 | 826 | compatible = "rockchip,px30-usb2phy"; |
819 | 827 | reg = <0x100 0x20>; |
820 | 828 | clocks = <&pmucru SCLK_USBPHY_REF>; |
|
1087 | 1095 | compatible = "rockchip,iommu"; |
1088 | 1096 | reg = <0x0 0xff460f00 0x0 0x100>; |
1089 | 1097 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
1090 | | - interrupt-names = "vopb_mmu"; |
1091 | 1098 | clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; |
1092 | 1099 | clock-names = "aclk", "iface"; |
1093 | 1100 | power-domains = <&power PX30_PD_VO>; |
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1128 | 1135 | compatible = "rockchip,iommu"; |
1129 | 1136 | reg = <0x0 0xff470f00 0x0 0x100>; |
1130 | 1137 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
1131 | | - interrupt-names = "vopl_mmu"; |
1132 | 1138 | clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; |
1133 | 1139 | clock-names = "aclk", "iface"; |
1134 | 1140 | power-domains = <&power PX30_PD_VO>; |
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