Skip to content

Commit 7f2fc18

Browse files
bchihiBLmbgg
bchihiBL
authored and
mbgg
committed
arm64: dts: mediatek: mt8195: Add temperature mitigation threshold
The mt8195 SoC has several hotspots around the CPUs. Specify the targeted temperature threshold when to apply the mitigation and define the associated cooling devices. Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230209105628.50294-7-bchihi@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
1 parent fd1c6f1 commit 7f2fc18

1 file changed

Lines changed: 153 additions & 16 deletions

File tree

‎arch/arm64/boot/dts/mediatek/mt8195.dtsi‎

Lines changed: 153 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
1515
#include <dt-bindings/power/mt8195-power.h>
1616
#include <dt-bindings/reset/mt8195-resets.h>
17+
#include <dt-bindings/thermal/thermal.h>
1718
#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
1819

1920
/ {
@@ -3002,107 +3003,243 @@
30023003

30033004
thermal_zones: thermal-zones {
30043005
cpu0-thermal {
3005-
polling-delay = <0>;
3006-
polling-delay-passive = <0>;
3006+
polling-delay = <1000>;
3007+
polling-delay-passive = <250>;
30073008
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3009+
30083010
trips {
3011+
cpu0_alert: trip-alert {
3012+
temperature = <85000>;
3013+
hysteresis = <2000>;
3014+
type = "passive";
3015+
};
3016+
30093017
cpu0_crit: trip-crit {
30103018
temperature = <100000>;
30113019
hysteresis = <2000>;
30123020
type = "critical";
30133021
};
30143022
};
3023+
3024+
cooling-maps {
3025+
map0 {
3026+
trip = <&cpu0_alert>;
3027+
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3028+
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3029+
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3030+
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3031+
};
3032+
};
30153033
};
30163034

30173035
cpu1-thermal {
3018-
polling-delay = <0>;
3019-
polling-delay-passive = <0>;
3036+
polling-delay = <1000>;
3037+
polling-delay-passive = <250>;
30203038
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3039+
30213040
trips {
3041+
cpu1_alert: trip-alert {
3042+
temperature = <85000>;
3043+
hysteresis = <2000>;
3044+
type = "passive";
3045+
};
3046+
30223047
cpu1_crit: trip-crit {
30233048
temperature = <100000>;
30243049
hysteresis = <2000>;
30253050
type = "critical";
30263051
};
30273052
};
3053+
3054+
cooling-maps {
3055+
map0 {
3056+
trip = <&cpu1_alert>;
3057+
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3058+
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3059+
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3060+
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3061+
};
3062+
};
30283063
};
30293064

30303065
cpu2-thermal {
3031-
polling-delay = <0>;
3032-
polling-delay-passive = <0>;
3066+
polling-delay = <1000>;
3067+
polling-delay-passive = <250>;
30333068
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3069+
30343070
trips {
3071+
cpu2_alert: trip-alert {
3072+
temperature = <85000>;
3073+
hysteresis = <2000>;
3074+
type = "passive";
3075+
};
3076+
30353077
cpu2_crit: trip-crit {
30363078
temperature = <100000>;
30373079
hysteresis = <2000>;
30383080
type = "critical";
30393081
};
30403082
};
3083+
3084+
cooling-maps {
3085+
map0 {
3086+
trip = <&cpu2_alert>;
3087+
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3088+
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3089+
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3090+
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3091+
};
3092+
};
30413093
};
30423094

30433095
cpu3-thermal {
3044-
polling-delay = <0>;
3045-
polling-delay-passive = <0>;
3096+
polling-delay = <1000>;
3097+
polling-delay-passive = <250>;
30463098
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3099+
30473100
trips {
3101+
cpu3_alert: trip-alert {
3102+
temperature = <85000>;
3103+
hysteresis = <2000>;
3104+
type = "passive";
3105+
};
3106+
30483107
cpu3_crit: trip-crit {
30493108
temperature = <100000>;
30503109
hysteresis = <2000>;
30513110
type = "critical";
30523111
};
30533112
};
3113+
3114+
cooling-maps {
3115+
map0 {
3116+
trip = <&cpu3_alert>;
3117+
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3118+
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3119+
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3120+
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3121+
};
3122+
};
30543123
};
30553124

30563125
cpu4-thermal {
3057-
polling-delay = <0>;
3058-
polling-delay-passive = <0>;
3126+
polling-delay = <1000>;
3127+
polling-delay-passive = <250>;
30593128
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3129+
30603130
trips {
3131+
cpu4_alert: trip-alert {
3132+
temperature = <85000>;
3133+
hysteresis = <2000>;
3134+
type = "passive";
3135+
};
3136+
30613137
cpu4_crit: trip-crit {
30623138
temperature = <100000>;
30633139
hysteresis = <2000>;
30643140
type = "critical";
30653141
};
30663142
};
3143+
3144+
cooling-maps {
3145+
map0 {
3146+
trip = <&cpu4_alert>;
3147+
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3148+
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3149+
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3150+
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3151+
};
3152+
};
30673153
};
30683154

30693155
cpu5-thermal {
3070-
polling-delay = <0>;
3071-
polling-delay-passive = <0>;
3156+
polling-delay = <1000>;
3157+
polling-delay-passive = <250>;
30723158
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3159+
30733160
trips {
3161+
cpu5_alert: trip-alert {
3162+
temperature = <85000>;
3163+
hysteresis = <2000>;
3164+
type = "passive";
3165+
};
3166+
30743167
cpu5_crit: trip-crit {
30753168
temperature = <100000>;
30763169
hysteresis = <2000>;
30773170
type = "critical";
30783171
};
30793172
};
3173+
3174+
cooling-maps {
3175+
map0 {
3176+
trip = <&cpu5_alert>;
3177+
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3178+
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3179+
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3180+
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3181+
};
3182+
};
30803183
};
30813184

30823185
cpu6-thermal {
3083-
polling-delay = <0>;
3084-
polling-delay-passive = <0>;
3186+
polling-delay = <1000>;
3187+
polling-delay-passive = <250>;
30853188
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3189+
30863190
trips {
3191+
cpu6_alert: trip-alert {
3192+
temperature = <85000>;
3193+
hysteresis = <2000>;
3194+
type = "passive";
3195+
};
3196+
30873197
cpu6_crit: trip-crit {
30883198
temperature = <100000>;
30893199
hysteresis = <2000>;
30903200
type = "critical";
30913201
};
30923202
};
3203+
3204+
cooling-maps {
3205+
map0 {
3206+
trip = <&cpu6_alert>;
3207+
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3208+
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3209+
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3210+
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3211+
};
3212+
};
30933213
};
30943214

30953215
cpu7-thermal {
3096-
polling-delay = <0>;
3097-
polling-delay-passive = <0>;
3216+
polling-delay = <1000>;
3217+
polling-delay-passive = <250>;
30983218
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3219+
30993220
trips {
3221+
cpu7_alert: trip-alert {
3222+
temperature = <85000>;
3223+
hysteresis = <2000>;
3224+
type = "passive";
3225+
};
3226+
31003227
cpu7_crit: trip-crit {
31013228
temperature = <100000>;
31023229
hysteresis = <2000>;
31033230
type = "critical";
31043231
};
31053232
};
3233+
3234+
cooling-maps {
3235+
map0 {
3236+
trip = <&cpu7_alert>;
3237+
cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3238+
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3239+
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3240+
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3241+
};
3242+
};
31063243
};
31073244
};
31083245
};

0 commit comments

Comments
 (0)