Skip to content

Commit 8397c58

Browse files
bebarinobebarino
committed
Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next
 - Add Mediatek MT8196 clk drivers * clk-marvell: clk: mmp: pxa1908: Instantiate power driver through auxiliary bus * clk-xilinx: clk: clocking-wizard: Fix output clock register offset for Versal platforms clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver() * clk-mediatek: (31 commits) clk: mediatek: Add MT8196 vencsys clock support clk: mediatek: Add MT8196 vdecsys clock support clk: mediatek: Add MT8196 ovl1 clock support clk: mediatek: Add MT8196 ovl0 clock support clk: mediatek: Add MT8196 disp-ao clock support clk: mediatek: Add MT8196 disp1 clock support clk: mediatek: Add MT8196 disp0 clock support clk: mediatek: Add MT8196 mfg clock support clk: mediatek: Add MT8196 mdpsys clock support clk: mediatek: Add MT8196 mcu clock support clk: mediatek: Add MT8196 I2C clock support clk: mediatek: Add MT8196 pextpsys clock support clk: mediatek: Add MT8196 ufssys clock support clk: mediatek: Add MT8196 peripheral clock support clk: mediatek: Add MT8196 vlpckgen clock support clk: mediatek: Add MT8196 topckgen2 clock support clk: mediatek: Add MT8196 topckgen clock support clk: mediatek: Add MT8196 apmixedsys clock support dt-bindings: clock: mediatek: Describe MT8196 clock controllers clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro ... * clk-loongson: clk: loongson2: Add clock definitions for Loongson-2K0300 SoC clk: loongson2: Avoid hardcoding firmware name of the reference clock clk: loongson2: Allow zero divisors for dividers clk: loongson2: Support scale clocks with an alternative mode clk: loongson2: Allow specifying clock flags for gate clock dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
5 parents b91217d + a787ab5 + 7c2e86f + 2f66f06 + 74743c5 commit 8397c58

44 files changed

Lines changed: 6415 additions & 78 deletions

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml‎

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ description: |
1616
properties:
1717
compatible:
1818
enum:
19+
- loongson,ls2k0300-clk
1920
- loongson,ls2k0500-clk
2021
- loongson,ls2k-clk # This is for Loongson-2K1000
2122
- loongson,ls2k2000-clk
@@ -24,8 +25,7 @@ properties:
2425
maxItems: 1
2526

2627
clocks:
27-
items:
28-
- description: 100m ref
28+
maxItems: 1
2929

3030
clock-names:
3131
items:
@@ -38,11 +38,23 @@ properties:
3838
ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h
3939
for the full list of Loongson-2 SoC clock IDs.
4040

41+
allOf:
42+
- if:
43+
properties:
44+
compatible:
45+
contains:
46+
const: loongson,ls2k0300-clk
47+
then:
48+
properties:
49+
clock-names: false
50+
else:
51+
required:
52+
- clock-names
53+
4154
required:
4255
- compatible
4356
- reg
4457
- clocks
45-
- clock-names
4658
- '#clock-cells'
4759

4860
additionalProperties: false

‎Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml‎

Lines changed: 112 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,112 @@
1+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: MediaTek Functional Clock Controller for MT8196
8+
9+
maintainers:
10+
- Guangjie Song <guangjie.song@mediatek.com>
11+
- Laura Nao <laura.nao@collabora.com>
12+
13+
description: |
14+
The clock architecture in MediaTek SoCs is structured like below:
15+
PLLs -->
16+
dividers -->
17+
muxes
18+
-->
19+
clock gate
20+
21+
The device nodes provide clock gate control in different IP blocks.
22+
23+
properties:
24+
compatible:
25+
items:
26+
- enum:
27+
- mediatek,mt8196-imp-iic-wrap-c
28+
- mediatek,mt8196-imp-iic-wrap-e
29+
- mediatek,mt8196-imp-iic-wrap-n
30+
- mediatek,mt8196-imp-iic-wrap-w
31+
- mediatek,mt8196-mdpsys0
32+
- mediatek,mt8196-mdpsys1
33+
- mediatek,mt8196-pericfg-ao
34+
- mediatek,mt8196-pextp0cfg-ao
35+
- mediatek,mt8196-pextp1cfg-ao
36+
- mediatek,mt8196-ufscfg-ao
37+
- mediatek,mt8196-vencsys
38+
- mediatek,mt8196-vencsys-c1
39+
- mediatek,mt8196-vencsys-c2
40+
- mediatek,mt8196-vdecsys
41+
- mediatek,mt8196-vdecsys-soc
42+
- mediatek,mt8196-vdisp-ao
43+
- const: syscon
44+
45+
reg:
46+
maxItems: 1
47+
48+
'#clock-cells':
49+
const: 1
50+
51+
'#reset-cells':
52+
const: 1
53+
description:
54+
Reset lines for PEXTP0/1 and UFS blocks.
55+
56+
mediatek,hardware-voter:
57+
$ref: /schemas/types.yaml#/definitions/phandle
58+
description: |
59+
Phandle to the "Hardware Voter" (HWV), as named in the vendor
60+
documentation for MT8196/MT6991.
61+
62+
The HWV is a SoC-internal fixed-function MCU used to collect votes from
63+
both the Application Processor and other remote processors within the SoC.
64+
It is intended to transparently enable or disable hardware resources (such
65+
as power domains or clocks) based on internal vote aggregation handled by
66+
the MCU's internal state machine.
67+
68+
However, in practice, this design is incomplete. While the HWV performs
69+
some internal vote aggregation,software is still required to
70+
- Manually enable power supplies externally, if present and if required
71+
- Manually enable parent clocks via direct MMIO writes to clock controllers
72+
- Enable the FENC after the clock has been ungated via direct MMIO
73+
writes to clock controllers
74+
75+
As such, the HWV behaves more like a hardware-managed clock reference
76+
counter than a true voter. Furthermore, it is not a separate
77+
controller. It merely serves as an alternative interface to the same
78+
underlying clock or power controller. Actual control still requires
79+
direct access to the controller's own MMIO register space, in
80+
addition to writing to the HWV's MMIO region.
81+
82+
For this reason, a custom phandle is used here - drivers need to directly
83+
access the HWV MMIO region in a syscon-like fashion, due to how the
84+
hardware is wired. This differs from true hardware voting systems, which
85+
typically do not require custom phandles and rely instead on generic APIs
86+
(clocks, power domains, interconnects).
87+
88+
The name "hardware-voter" is retained to match vendor documentation, but
89+
this should not be reused or misunderstood as a proper voting mechanism.
90+
91+
required:
92+
- compatible
93+
- reg
94+
- '#clock-cells'
95+
96+
additionalProperties: false
97+
98+
examples:
99+
- |
100+
pericfg_ao: clock-controller@16640000 {
101+
compatible = "mediatek,mt8196-pericfg-ao", "syscon";
102+
reg = <0x16640000 0x1000>;
103+
mediatek,hardware-voter = <&scp_hwv>;
104+
#clock-cells = <1>;
105+
};
106+
- |
107+
pextp0cfg_ao: clock-controller@169b0000 {
108+
compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon";
109+
reg = <0x169b0000 0x1000>;
110+
#clock-cells = <1>;
111+
#reset-cells = <1>;
112+
};

‎Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml‎

Lines changed: 107 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,107 @@
1+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: MediaTek System Clock Controller for MT8196
8+
9+
maintainers:
10+
- Guangjie Song <guangjie.song@mediatek.com>
11+
- Laura Nao <laura.nao@collabora.com>
12+
13+
description: |
14+
The clock architecture in MediaTek SoCs is structured like below:
15+
PLLs -->
16+
dividers -->
17+
muxes
18+
-->
19+
clock gate
20+
21+
The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll
22+
provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.
23+
The topckgen, topckgen_gp2 and vlpckgen provide dividers and muxes which
24+
provide the clock source to other IP blocks.
25+
26+
properties:
27+
compatible:
28+
items:
29+
- enum:
30+
- mediatek,mt8196-apmixedsys
31+
- mediatek,mt8196-armpll-b-pll-ctrl
32+
- mediatek,mt8196-armpll-bl-pll-ctrl
33+
- mediatek,mt8196-armpll-ll-pll-ctrl
34+
- mediatek,mt8196-apmixedsys-gp2
35+
- mediatek,mt8196-ccipll-pll-ctrl
36+
- mediatek,mt8196-mfgpll-pll-ctrl
37+
- mediatek,mt8196-mfgpll-sc0-pll-ctrl
38+
- mediatek,mt8196-mfgpll-sc1-pll-ctrl
39+
- mediatek,mt8196-ptppll-pll-ctrl
40+
- mediatek,mt8196-topckgen
41+
- mediatek,mt8196-topckgen-gp2
42+
- mediatek,mt8196-vlpckgen
43+
- const: syscon
44+
45+
reg:
46+
maxItems: 1
47+
48+
'#clock-cells':
49+
const: 1
50+
51+
mediatek,hardware-voter:
52+
$ref: /schemas/types.yaml#/definitions/phandle
53+
description: |
54+
Phandle to the "Hardware Voter" (HWV), as named in the vendor
55+
documentation for MT8196/MT6991.
56+
57+
The HWV is a SoC-internal fixed-function MCU used to collect votes from
58+
both the Application Processor and other remote processors within the SoC.
59+
It is intended to transparently enable or disable hardware resources (such
60+
as power domains or clocks) based on internal vote aggregation handled by
61+
the MCU's internal state machine.
62+
63+
However, in practice, this design is incomplete. While the HWV performs
64+
some internal vote aggregation,software is still required to
65+
- Manually enable power supplies externally, if present and if required
66+
- Manually enable parent clocks via direct MMIO writes to clock controllers
67+
- Enable the FENC after the clock has been ungated via direct MMIO
68+
writes to clock controllers
69+
70+
As such, the HWV behaves more like a hardware-managed clock reference
71+
counter than a true voter. Furthermore, it is not a separate
72+
controller. It merely serves as an alternative interface to the same
73+
underlying clock or power controller. Actual control still requires
74+
direct access to the controller's own MMIO register space, in
75+
addition to writing to the HWV's MMIO region.
76+
77+
For this reason, a custom phandle is used here - drivers need to directly
78+
access the HWV MMIO region in a syscon-like fashion, due to how the
79+
hardware is wired. This differs from true hardware voting systems, which
80+
typically do not require custom phandles and rely instead on generic APIs
81+
(clocks, power domains, interconnects).
82+
83+
The name "hardware-voter" is retained to match vendor documentation, but
84+
this should not be reused or misunderstood as a proper voting mechanism.
85+
86+
required:
87+
- compatible
88+
- reg
89+
- '#clock-cells'
90+
91+
additionalProperties: false
92+
93+
examples:
94+
- |
95+
apmixedsys_clk: syscon@10000800 {
96+
compatible = "mediatek,mt8196-apmixedsys", "syscon";
97+
reg = <0x10000800 0x1000>;
98+
#clock-cells = <1>;
99+
};
100+
- |
101+
topckgen: syscon@10000000 {
102+
compatible = "mediatek,mt8196-topckgen", "syscon";
103+
reg = <0x10000000 0x800>;
104+
mediatek,hardware-voter = <&scp_hwv>;
105+
#clock-cells = <1>;
106+
};
107+

‎MAINTAINERS‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2869,7 +2869,9 @@ ARM/Marvell PXA1908 SOC support
28692869
M: Duje Mihanović <duje@dujemihanovic.xyz>
28702870
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
28712871
S: Maintained
2872+
F: Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
28722873
F: arch/arm64/boot/dts/marvell/mmp/
2874+
F: drivers/clk/mmp/Kconfig
28732875
F: drivers/clk/mmp/clk-pxa1908*.c
28742876
F: include/dt-bindings/clock/marvell,pxa1908.h
28752877

‎drivers/clk/Kconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -512,6 +512,7 @@ source "drivers/clk/imx/Kconfig"
512512
source "drivers/clk/ingenic/Kconfig"
513513
source "drivers/clk/keystone/Kconfig"
514514
source "drivers/clk/mediatek/Kconfig"
515+
source "drivers/clk/mmp/Kconfig"
515516
source "drivers/clk/meson/Kconfig"
516517
source "drivers/clk/mstar/Kconfig"
517518
source "drivers/clk/microchip/Kconfig"

0 commit comments

Comments
 (0)